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| hitachi single-chip microcomputer h8/329 series h8/329 hd6473298, hd6433298, hd6413298 h8/328 hd6433288 h8/327 hd6473278, hd6433278, hd6413278 h8/326 hd6433268 hardware manual omc942723054
preface the h8/329 series is a series of high-performance single-chip microcomputers having a fast h8/300 cpu core and a set of on-chip supporting functions optimized for embedded control. these include rom, ram, two types of timers, a serial communication interface, an a/d converter, i/o ports, and other functions needed in control system configurations, so that compact, high-performance systems can be realized easily. the h8/329 series includes four chips: the h8/329 with 32k-byte rom and 1k-byte ram; the h8/328 with 24k-byte rom and 1k-byte ram; the h8/327 with 16k-byte rom and 512-byte ram; and the h8/326 with 8k-byte rom and 256-byte ram. the h8/329 and h8/327 are available in a masked rom version, a ztat * (zero turn-around time) version, and a romless version, providing a quick and flexible response to conditions from ramp-up through full-scale volume producion, even for applications with frequently-changing specifications. this manual describes the hardware of the h8/329 series. refer to the h8/300 series programming manual for a detailed description of the instruction set. notes: * ztat is a registered trademark of hitachi, ltd. contents section 1. overview ............................................................................................................... 1 1.1 overview............................................................................................................................... 1 1.2 block diagram...................................................................................................................... 5 1.3 pin assignments and functions............................................................................................ 6 1.3.1 pin arrangement...................................................................................................... 6 1.3.2 pin functions ........................................................................................................... 8 section 2. mcu operating modes and address space ................................................ 15 2.1 overview............................................................................................................................... 15 2.1.1 mode selection ........................................................................................................ 15 2.1.2 mode and system control registers (mdcr and syscr) ................................... 16 2.2 system control register (syscr)?'ffc4 ...................................................................... 16 2.3 mode control register (mdcr)?'ffc5 ......................................................................... 18 2.4 address space maps............................................................................................................. 19 section 3. cpu ........................................................................................................................ 23 3.1 overview............................................................................................................................... 23 3.1.1 features.................................................................................................................... 23 3.2 register configuration.......................................................................................................... 24 3.2.1 general registers..................................................................................................... 24 3.2.2 control registers ..................................................................................................... 25 3.2.3 initial register values.............................................................................................. 26 3.3 addressing modes ................................................................................................................ 27 3.3.1 addressing mode..................................................................................................... 27 3.3.2 how to calculate where the execution starts ........................................................ 29 3.4 data formats......................................................................................................................... 33 3.4.1 data formats in general registers.......................................................................... 34 3.4.2 memory data formats............................................................................................. 35 3.5 instruction set ....................................................................................................................... 36 3.5.1 data transfer instructions ....................................................................................... 38 3.5.2 arithmetic operations ............................................................................................. 40 3.5.3 logic operations ..................................................................................................... 41 3.5.4 shift operations....................................................................................................... 41 3.5.5 bit manipulations .................................................................................................... 43 3.5.6 branching instructions............................................................................................. 47 3.5.7 system control instructions .................................................................................... 49 i 3.5.8 block data transfer instruction .............................................................................. 50 3.6 cpu states ............................................................................................................................ 51 3.6.1 program execution state ......................................................................................... 52 3.6.2 exception-handling state........................................................................................ 52 3.6.3 power-down state ................................................................................................... 53 3.7 access timing and bus cycle .............................................................................................. 53 3.7.1 access to on-chip memory (ram and rom) ...................................................... 53 3.7.2 access to on-chip register field and external devices ........................................ 55 section 4. exception handling ............................................................................................ 59 4.1 overview............................................................................................................................... 59 4.2 reset ..................................................................................................................................... 59 4.2.1 overview ................................................................................................................. 59 4.2.2 reset sequence ........................................................................................................ 59 4.2.3 disabling of interrupts after reset........................................................................... 62 4.3 interrupts............................................................................................................................... 62 4.3.1 overview ................................................................................................................. 62 4.3.2 interrupt-related registers...................................................................................... 64 4.3.3 external interrupts ................................................................................................... 66 4.3.4 internal interrupts .................................................................................................... 67 4.3.5 interrupt handling ................................................................................................... 67 4.3.6 interrupt response time.......................................................................................... 72 4.3.7 precaution ................................................................................................................ 72 4.4 note on stack handling........................................................................................................ 73 section 5. i/o ports ................................................................................................................ 75 5.1 overview............................................................................................................................... 75 5.2 port 1..................................................................................................................................... 77 5.3 port 2..................................................................................................................................... 80 5.4 port 3..................................................................................................................................... 84 5.5 port 4..................................................................................................................................... 88 5.6 port 5..................................................................................................................................... 96 5.7 port 6..................................................................................................................................... 100 5.8 port 7..................................................................................................................................... 111 section 6. 16-bit free-running timer .............................................................................. 113 6.1 overview............................................................................................................................... 113 6.1.1 features.................................................................................................................... 113 ii 6.1.2 block diagram......................................................................................................... 113 6.1.3 input and output pins .............................................................................................. 115 6.1.4 register configuration ............................................................................................ 115 6.2 register descriptions............................................................................................................ 116 6.2.1 free-running counter (frc)?'ff92.................................................................. 116 6.2.2 output compare registers a and b (ocra and ocrb)?'ff94....................... 117 6.2.3 input capture registers a to d (icra to icrd) h'ff98, h'ff9a, h'ff9c, h'ff9e ......................................................................... 117 6.2.4 timer interrupt enable register (tier)?'ff90 ................................................. 120 6.2.5 timer control/status register (tcsr)?'ff91 ................................................... 122 6.2.6 timer control register (tcr)?'ff96 ................................................................ 125 6.2.7 timer output compare control register (tocr)?'ff97.................................. 127 6.3 cpu interface ....................................................................................................................... 128 6.4 operation .............................................................................................................................. 130 6.4.1 frc incrementation timing.................................................................................... 130 6.4.2 output compare timing.......................................................................................... 132 6.4.3 input capture timing .............................................................................................. 133 6.4.4 setting of frc overflow flag (ovf)..................................................................... 136 6.5 interrupts............................................................................................................................... 137 6.6 sample application............................................................................................................... 137 6.7 application notes ................................................................................................................. 138 section 7. 8-bit timers ......................................................................................................... 143 7.1 overview............................................................................................................................... 143 7.1.1 features.................................................................................................................... 143 7.1.2 block diagram......................................................................................................... 143 7.1.3 input and output pins .............................................................................................. 144 7.1.4 register configuration ............................................................................................ 145 7.2 register descriptions............................................................................................................ 145 7.2.1 timer counter (tcnt)?'ffcc (tmr0), h'ffd4 (tmr1)............................... 145 7.2.2 time constant registers a and b (tcora and tcorb) h'ffca and h'ffcb (tmr0), h'ffd2 and h'ffd3 (tmr1) .............................. 146 7.2.3 timer control register (tcr)?'ffc8 (tmr0), h'ffd0 (tmr1) .................... 146 7.2.4 timer control/status register (tcsr)?'ffc9 (tmr0), h'ffd1 (tmr1) ....... 149 7.2.5 serial/timer control register (stcr)?'ffc3 ................................................... 151 7.3 operation .............................................................................................................................. 152 7.3.1 tcnt incrementation timing................................................................................. 152 7.3.2 compare match timing........................................................................................... 153 iii 7.3.3 external reset of tcnt .......................................................................................... 155 7.3.4 setting of tcsr overflow flag (ovf) .................................................................. 156 7.4 interrupts............................................................................................................................... 157 7.5 sample application............................................................................................................... 157 7.6 application notes ................................................................................................................. 158 section 8. serial communication interface ..................................................................... 163 8.1 overview............................................................................................................................... 163 8.1.1 features.................................................................................................................... 163 8.1.2 block diagram......................................................................................................... 164 8.1.3 input and output pins .............................................................................................. 164 8.1.4 register configuration ............................................................................................ 165 8.2 register descriptions............................................................................................................ 166 8.2.1 receive shift register (rsr) .................................................................................. 166 8.2.2 receive data register (rdr)?'ffdd................................................................ 166 8.2.3 transmit shift register (tsr)................................................................................. 166 8.2.4 transmit data register (tdr)?'ffdb............................................................... 167 8.2.5 serial mode register (smr)?'ffd8 .................................................................. 167 8.2.6 serial control register (scr)?'ffda ............................................................... 170 8.2.7 serial status register (ssr)?'ffdc .................................................................. 174 8.2.8 bit rate register (brr)?'ffd9 ......................................................................... 177 8.2.9 serial/timer control register (stcr)?'ffc3 ................................................... 181 8.3 operation .............................................................................................................................. 182 8.3.1 overview ................................................................................................................. 182 8.3.2 asynchronous mode................................................................................................ 184 8.3.3 clocked synchronous operation ............................................................................. 197 8.4 sci interrupts........................................................................................................................ 206 8.5 application notes ................................................................................................................. 206 section 9. a/d converter ..................................................................................................... 209 9.1 overview............................................................................................................................... 209 9.1.1 features.................................................................................................................... 209 9.1.2 block diagram......................................................................................................... 210 9.1.3 input pins................................................................................................................. 211 9.1.4 register configuration ............................................................................................ 211 9.2 register descriptions............................................................................................................ 212 9.2.1 a/d data registers (addr)?'ffe0 to h'ffe6................................................. 212 9.2.2 a/d control/status register (adcsr)?'ffe8 .................................................. 212 iv 9.2.3 a/d control register (adcr)?'ffea............................................................... 215 9.3 operation .............................................................................................................................. 215 9.3.1 single mode (scan = 0) ........................................................................................ 216 9.3.2 scan mode (scan = 1) .......................................................................................... 219 9.3.3 input sampling time and a/d conversion time.................................................... 222 9.3.4 external trigger input timing................................................................................. 223 9.4 interrupts............................................................................................................................... 224 section 10. ram ....................................................................................................................... 225 10.1 overview............................................................................................................................... 225 10.2 block diagram...................................................................................................................... 225 10.3 ram enable bit (rame) in system control register (syscr) ....................................... 225 10.4 operation .............................................................................................................................. 226 10.4.1 expanded modes (modes 1 and 2) .......................................................................... 226 10.4.2 single-chip mode (mode 3) ................................................................................... 226 section 11. rom ....................................................................................................................... 227 11.1 overview............................................................................................................................... 227 11.1.1 block diagram......................................................................................................... 228 11.2 prom mode (h8/329, h8/327) ........................................................................................... 228 11.2.1 prom mode setup ................................................................................................. 228 11.2.2 socket adapter pin assignments and memory map............................................... 229 11.3 programming ........................................................................................................................ 232 11.3.1 writing and verifying .............................................................................................. 232 11.3.2 notes on writing...................................................................................................... 236 11.3.3 reliability of written data ...................................................................................... 236 11.3.4 erasing of data ........................................................................................................ 237 11.4 handling of windowed packages......................................................................................... 238 section 12. power-down state .............................................................................................. 239 12.1 overview............................................................................................................................... 239 12.2 system control register: power-down control bits ........................................................... 240 12.3 sleep mode ........................................................................................................................... 241 12.3.1 transition to sleep mode......................................................................................... 242 12.3.2 exit from sleep mode ............................................................................................. 242 12.4 software standby mode........................................................................................................ 242 12.4.1 transition to software standby mode..................................................................... 243 12.4.2 exit from software standby mode.......................................................................... 243 v 12.4.3 sample application of software standby mode ..................................................... 243 12.4.4 application note ..................................................................................................... 244 12.5 hardware standby mode ...................................................................................................... 245 12.5.1 transition to hardware standby mode.................................................................... 245 12.5.2 recovery from hardware standby mode................................................................ 245 12.5.3 timing relationships............................................................................................... 246 section 13. clock pulse generator ....................................................................................... 247 13.1 overview............................................................................................................................... 247 13.1.1 block diagram......................................................................................................... 247 13.2 oscillator circuit................................................................................................................... 247 13.3 system clock divider........................................................................................................... 250 section 14. electrical specifications .................................................................................... 251 14.1 absolute maximum ratings ................................................................................................. 251 14.2 electrical characteristics ...................................................................................................... 251 14.2.1 dc characteristics................................................................................................... 251 14.2.2 ac characteristics................................................................................................... 257 14.2.3 a/d converter characteristics................................................................................. 261 14.3 mcu operational timing..................................................................................................... 262 14.3.1 bus timing .............................................................................................................. 262 14.3.2 control signal timing ............................................................................................. 263 14.3.3 16-bit free-running timer timing ........................................................................ 266 14.3.4 8-bit timer timing.................................................................................................. 267 14.3.5 serial communication interface timing ................................................................. 268 14.3.6 i/o port timing........................................................................................................ 269 appendices appendix a. cpu instruction set ...................................................................................... 271 a.1 instruction set list................................................................................................................ 271 a.2 operation code map............................................................................................................. 278 a.3 number of states required for execution............................................................................ 280 appendix b. register field ................................................................................................. 286 b.1 register addresses and bit names....................................................................................... 286 b.2 register descriptions............................................................................................................ 290 vi appendix c. pin states ......................................................................................................... 317 c.1 pin states in each mode ....................................................................................................... 317 appendix d. timing of transition to and recovery from hardware standby mode ................................................................................................ 319 appendix e. package dimensions .................................................................................... 320 vii section 1. overview 1.1 overview the h8/329 series of single-chip microcomputers features an h8/300 cpu core and a complement of on-chip supporting modules implementing a variety of system functions. the h8/300 cpu is a high-speed processor with an architecture featuring powerful bit- manipulation instructions, ideally suited for realtime control applications. the on-chip supporting modules implement peripheral functions needed in system configurations. these include rom, ram, two types of timers (a 16-bit free-running timer and 8-bit timers), a serial communication interface (sci), an a/d converter, and i/o ports. the h8/329 series can operate in a single-chip mode or in two expanded modes, depending on the requirements of the application. (the operating mode will be referred to as the mcu mode in this manual.) the entire h8/329 series is available with masked rom. the h8/329 and h8/327 are also available in ztat versions* that can be programmed at the user site, and in romless versions. notes: * ztat is a registered trademark of hitachi, ltd. table 1-1 lists the features of the h8/329 series. 1 table 1-1. features item specification cpu two-way general register configuration eight 16-bit registers, or sixteen 8-bit registers high-speed operation maximum clock rate: 10mhz add/subtract: 0.2 s multiply/divide: 1.4 s streamlined, concise instruction set instruction length: 2 or 4 bytes register-register arithmetic and logic operations mov instruction for data transfer between registers and memory instruction set features multiply instruction (8 bits 8 bits) divide instruction (16 bits 8 bits) bit-accumulator instructions register-indirect specification of bit positions memory h8/329: 32k-byte rom; 1k-byte ram h8/328: 24k-byte rom; 1k-byte ram h8/327: 16k-byte rom; 512-byte ram h8/326: 8k-byte rom; 256-byte ram 16-bit free- one 16-bit free-running counter (can also count external events) running timer two output-compare lines (1 channel) four input capture lines (can be buffered) 8-bit timer each channel has (2 channels) one 8-bit up-counter (can also count external events) two time constant registers serial asynchronous or clocked synchronous mode (selectable) communication full duplex: can transmit and receive simultaneously interface (sci) on-chip baud rate generator (1 channel) 2 table 1-1. features (cont.) item specification a/d converter 8-bit resolution eight channels: single or scan mode (selectable) start of a/d conversion can be externally triggered sample-and-hold function i/o ports 43 input/output lines (16 of which can drive leds) 8 input-only lines interrupts four external interrupt lines: nmi, irq 0 , irq 1 , irq 2 18 on-chip interrupt sources operating expanded mode with on-chip rom disabled (mode 1) modes expanded mode with on-chip rom enabled (mode 2) single-chip mode (mode 3) power-down sleep mode modes software standby mode hardware standby mode other features on-chip oscillator 3 table 1-1. features (cont.) item specification series lineup 5-v version 3-v version package rom h8/329 hd6473298c hd6473298vc 64-pin windowed shrink dip prom (dc-64s) hd6473298p hd6473298vp 64-pin shrink dip (dp-64s) hd6473298f hd6473298vf 64-pin qfp (fp-64a) hd6473298cp hd6473298vcp 68-pin plcc (cp-68) hd6433298p hd6433298vp 64-pin shrink dip (dp-64s) masked rom hd6433298f hd6433298vf 64-pin qfp (fp-64a) hd6433298cp hd6433298vcp 68-pin plcc (cp-68) hd6413298p hd6413298vp 64-pin shrink dip (dp-64s) romless hd6413298f hd6413298vf 64-pin qfp (fp-64a) hd6413298cp hd6413298vcp 68-pin plcc (cp-68) h8/328 hd6433288p hd6433288vp 64-pin shrink dip (dp-64s) masked rom hd6433288f hd6433288vf 64-pin qfp (fp-64a) HD6433288CP hd6433288vcp 68-pin plcc (cp-68) h8/327 hd6473278c hd6473278vc 64-pin windowed shrink dip prom (dc-64s) hd6473278p hd6473278vp 64-pin shrink dip (dp-64s) hd6473278f hd6473278vf 64-pin qfp (fp-64a) hd6473278cp hd6473278vcp 68-pin plcc (cp-68) hd6433278p hd6433278vp 64-pin shrink dip (dp-64s) masked rom hd6433278f hd6433278vf 64-pin qfp (fp-64a) hd6433278cp hd6433278vcp 68-pin plcc (cp-68) hd6413278p hd6413278vp 64-pin shrink dip (dp-64s) romless hd6413278f hd6413278vf 64-pin qfp (fp-64a) hd6413278cp hd6413278vcp 68-pin plcc (cp-68) h8/326 hd6433268p hd6433268vp 64-pin shrink dip (dp-64s) masked rom hd6433268f hd6433268vf 64-pin qfp (fp-64a) hd6433268cp hd6433268vcp 68-pin plcc (cp-68) 4 1.2 block diagram figure 1-1 shows a block diagram of the h8/329 series. figure 1-1. block diagram clock pulse gener- ator port 6 port 7 port 5 port 3 port 4 port 2 port 1 cpu h8/300 ram 16-bit free- running timer prom (or masked rom) serial communication interface 8-bit a/d converter (8 channels) 8-bit timer (2 channels) p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a 0 1 8 9 av cc av ss p3 7 /d 7 p3 6 /d 6 p3 5 /d 5 p3 4 /d 4 p3 3 /d 3 p3 2 /d 2 p3 1 /d 1 p3 0 /d 0 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 res md 1 md 0 v cc stby nmi v cc v ss v ss v ss v ss v ss v ss xtal extal p4 /irq /adtrg p4 /irq p4 /irq p4 /rd p4 /wr p4 /as p4 / p4 /wait * 1 * 2 0 1 2 3 4 5 6 7 2 1 0 notes: * * memory sizes h8/328 24k bytes 1k byte h8/327 16k bytes 512 bytes h8/326 8k bytes 256 bytes rom ram 1 2 cp-68 package only. prom is available only in the h8/329 and h8/327. h8/329 32k bytes 1k byte data bus (high) address bus 2 3 4 5 6 7 10 11 12 13 14 15 p6 /ftci/tmci p6 /ftoa p6 /ftia p6 /ftib/tmri p6 /ftic/tmo p6 /ftid/tmci p6 /ftob/tmri p6 /tmo 0 0 1 2 0 0 1 1 1 3 4 5 6 7 p7 /an p7 /an p7 /an p7 /an p7 /an p7 /an p7 /an p7 /an 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 p5 /txd p5 /rxd p5 /sck 0 1 2 data bus (low) 5 1.3 pin assignments and functions 1.3.1 pin arrangement figure 1-2 shows the pin arrangement of the dc-64s and dp-64s packages. figure 1-3 shows the pin arrangement of the fp-64a package. figure 1-4 shows the pin arrangement of the cp-68 package. figure 1-2. pin arrangement (dc-64s and dp-64s, top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p4 0 /adtrg/irq 2 p4 1 /irq 1 p4 2 /irq 0 p4 3 /rd p4 4 /wr p4 5 /as p4 6 / p4 7 /wait p5 0 /txd p5 1 /rxd p5 2 /sck res nmi v cc stby v ss xtal extal md 1 md 0 av ss p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 av cc p6 0 /ftci/tmci 0 p6 1 /ftoa p3 7 /d 7 p3 6 /d 6 p3 5 /d 5 p3 4 /d 4 p3 3 /d 3 p3 2 /d 2 p3 1 /d 1 p3 0 /d 0 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 v cc p6 7 /tmo 1 p6 6 /ftob/tmri 1 p6 5 /ftid/tmci 1 p6 4 /ftic/tmo 0 p6 3 /ftib/tmri 0 p6 2 /ftia 6 figure 1-3. pin arrangement (fp-64a, top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p4 7 /wait p4 6 / p4 5 /as p4 4 /wr p4 3 /rd p4 2 /irq 0 p4 1 /irq 1 p4 0 /adtrg/irq 2 p3 7 /d 7 p3 6 /d 6 p3 5 /d 5 p3 4 /d 4 p3 3 /d 3 p3 2 /d 2 p3 1 /d 1 p3 0 /d 0 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 av cc p6 0 /ftci/tmci 0 p6 1 /ftoa p6 2 /ftia p6 3 /ftib/tmri 0 p6 4 /ftic/tmo 0 p6 5 /ftid/tmci 1 p6 6 /ftob/tmri 1 p6 7 /tmo 1 v cc p2 7 /a 15 p5 0 /txd p5 1 /rxd p5 2 /sck res nmi v cc stby v ss xtal extal md 1 md 0 av ss p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 h049 h8/329 u.m. fig. 1-3 7 figure 1-4. pin arrangement (cp-68, top view) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 p4 7 /wait p4 6 / p4 5 /as p4 4 /wr p4 3 /rd p4 2 /irq 0 p4 1 /irq 1 p4 0 /adtrg/irq 2 v ss p3 7 /d 7 p3 6 /d 6 p3 5 /d 5 p3 4 /d 4 p3 3 /d 3 p3 2 /d 2 p3 1 /d 1 p3 0 /d 0 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 av cc p6 0 /ftci/tmci 0 p6 1 /ftoa v ss p6 2 /ftia p6 3 /ftib/tmri 0 p6 4 /ftic/tmo 0 p6 5 /ftid/tmci 1 p6 6 /ftob/tmri 1 p6 7 /tmo 1 v cc p2 7 /a 15 p5 0 /txd p5 1 /rxd p5 2 /sck res nmi v cc stby v ss v ss xtal extal md 1 md 0 av ss p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 h049 h8/329 u.m. fig. 1-4 8 1.3.2 pin functions (1) pin assignments in each operating mode: table 1-2 lists the assignments of the pins of the dc-64s, dp-64s, fp-64a, and cp-68 packages in each operating mode. table 1-2. pin assignments in each operating mode (1) pin no. dc-64s expanded modes single-chip mode prom dp-64s fp-64a cp-68 mode 1 mode 2 mode 3 mode 1 v ss v ss v ss v ss 1 57 2 p4 0 /irq 2 /adtrg p4 0 /irq 2 /adtrg p4 0 /irq 2 /adtrg nc 2 58 3 p4 1 /irq 1 p4 1 /irq 1 p4 1 /irq 1 nc 3 59 4 p4 2 /irq 0 p4 2 /irq 0 p4 2 /irq 0 nc 4 60 5 rd rd p4 3 nc 5 61 6 wr wr p4 4 nc 6 62 7 as as p4 5 nc 7 63 8 p4 6 / nc 8 64 9 wait wait p4 7 nc 9 1 10 p5 0 /txd p5 0 /txd p5 0 /txd nc 10 2 11 p5 1 /rxd p5 1 /rxd p5 1 /rxd nc 11 3 12 p5 2 /sck p5 2 /sck p5 2 /sck nc 12 4 13 res res res v pp 13 5 14 nmi nmi nmi ea 9 14 6 15 v cc v cc v cc v cc 15 7 16 stby stby stby v ss 16 8 17 v ss v ss v ss v ss 18 v ss v ss v ss v ss 17 9 19 xtal xtal xtal nc 18 10 20 extal extal extal nc 19 11 21 md 1 md 1 md 1 v ss 20 12 22 md 0 md 0 md 0 v ss 21 13 23 av ss av ss av ss v ss 22 14 24 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 nc 23 15 25 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 nc 24 16 26 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 nc 25 17 27 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 nc 26 18 28 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 nc 27 19 29 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 nc 28 20 30 p7 6 /an 6 p7 6 /an 6 p7 6 /an 6 nc 29 21 31 p7 7 /an 7 p7 7 /an 7 p7 7 /an 7 nc notes: 1. pins marked nc should be left unconnected. 2. for details on prom mode, refer to 11.2, ?rom mode. 9 table 1-2. pin assignments in each operating mode (2) pin no. dc-64s expanded modes single-chip mode prom dp-64s fp-64a cp-68 mode 1 mode 2 mode 3 mode 30 22 32 av cc av cc av cc v cc 31 23 33 p6 0 /ftci/tmci 0 p6 0 /ftci/tmci 0 p6 0 /ftci/tmci 0 nc 32 24 34 p6 1 /ftoa p6 1 /ftoa p6 1 /ftoa nc 35 v ss v ss v ss v ss 33 25 36 p6 2 /ftia p6 2 /ftia p6 2 /ftia nc 34 26 37 p6 3 /ftib/tmri 0 p6 3 /ftib/tmri 0 p6 3 /ftib/tmri 0 v cc 35 27 38 p6 4 /ftic/tmo 0 p6 4 /ftic/tmo 0 p6 4 /ftic/tmo 0 v cc 36 28 39 p6 5 /ftid/tmci 1 p6 5 /ftid/tmci 1 p6 5 /ftid/tmci 1 nc 37 29 40 p6 6 /ftob/tmri 1 p6 6 /ftob/tmri 1 p6 6 /ftob/tmri 1 nc 38 30 41 p6 7 /tmo 1 p6 7 /tmo 1 p6 7 /tmo 1 nc 39 31 42 v cc v cc v cc v cc 40 32 43 a 15 a2 7 /a 15 p2 7 ce 41 33 44 a 14 p2 6 /a 14 p2 6 ea 14 42 34 45 a 13 p2 5 /a 13 p2 5 ea 13 43 35 46 a 12 p2 4 /a 12 p2 4 ea 12 44 36 47 a 11 p2 3 /a 11 p2 3 ea 11 45 37 48 a 10 p2 2 /a 10 p2 2 ea 10 46 38 49 a 9 p2 1 /a 9 p2 1 oe 47 39 50 a 8 p2 0 /a 8 p2 0 ea 8 48 40 51 v ss v ss v ss v ss 52 v ss v ss v ss v ss 49 41 53 a 7 p1 7 /a 7 p1 7 ea 7 50 42 54 a 6 p1 6 /a 6 p1 6 ea 6 51 43 55 a 5 p1 5 /a 5 p1 5 ea 5 52 44 56 a 4 p1 4 /a 4 p1 4 ea 4 53 45 57 a 3 p1 3 /a 3 p1 3 ea 3 54 46 58 a 2 p1 2 /a 2 p1 2 ea 2 55 47 59 a 1 p1 1 /a 1 p1 1 ea 1 56 48 60 a 0 p1 0 /a 0 p1 0 ea 0 57 49 61 d 0 d 0 p3 0 eo 0 58 50 62 d 1 d 1 p3 1 eo 1 59 51 63 d 2 d 2 p3 2 eo 2 60 52 64 d 3 d 3 p3 3 eo 3 61 53 65 d 4 d 4 p3 4 eo 4 62 54 66 d 5 d 5 p3 5 eo 5 63 55 67 d 6 d 6 p3 6 eo 6 64 56 68 d 7 d 7 p3 7 eo 7 notes: 1. pins marked nc should be left unconnected. 2. for details on prom mode, refer to 11.2, ?rom mode. 10 (2) pin functions: table 1-3 gives a concise description of the function of each pin. table 1-3. pin functions (1) pin no. dc-64s type symbol dp-64s fp-64a cp-68 i/o name and function power v cc 14, 39 6, 31 15, 42 i power: connected to the power supply (+5v). connect both v cc pins to the system power supply (+5v). v ss 16, 48 8, 40 1, 17, 18, i ground: connected to ground (0v). 35, 51, 52 connect all vss pins to the system power supply (0v). clock xtal 17 9 19 i crystal: connected to a crystal oscillator. the crystal frequency should be double the desired system clock frequency. if an external clock is input at the extal pin, a reverse-phase clock should be input at the xtal pin. extal 18 10 20 i external crystal: connected to a crystal oscillator or external clock. the frequency of the external clock should be double the desired system clock frequency. see section 13.2, ?scillator circuit?for examples of connections to a crystal and external clock. 7 63 8 o system clock: supplies the system clock to peripheral devices. system res 12 4 13 i reset: a low input causes the chip to control reset. stby 15 7 16 i standby: a transition to the hardware standby mode (a power-down state) occurs when a low input is received at the stby pin. address a 15 to a 0 40 to 47, 32 to 39, 43 to 50, o address bus: address output pins. bus 49 to 56 41 to 48 53 to 60 11 table 1-3. pin functions (2) pin no. dc-64s type symbol dp-64s fp-64a cp-68 i/o name and function data bus d 7 to d 0 57 to 64 49 to 56 61 to 68 i/o data bus: 8-bit bidirectional data bus. bus wait 8 64 9 i wait: requests the cpu to insert t w control states into the bus cycle when an external address is accessed. rd 4 60 5 o read: goes low to indicate that the cpu is reading an external address. wr 5 61 6 o write: goes low to indicate that the cpu is writing to an external address. as 6 62 7 o address strobe: goes low to indicate that there is a valid address on the address bus. interrupt nmi 13 5 14 i nonmaskable interrupt: highest- signals priority interrupt request. the nmieg bit in the system control register (syscr) determines whether the interrupt is requested on the rising or falling edge of the nmi input. irq 0 to 1 to 3 57 to 59 2 to 4 i interrupt request 0 to 2: maskable irq 2 interrupt request pins. operating md 1 , 19, 11, 21, i mode: input pins for setting the mcu mode md 0 20 12 22 operating mode according to the table control below. md 1 md 0 mode description 0 1 mode 1 expanded mode with on-chip rom disabled 1 0 mode 2 expanded mode with on-chip rom enabled 1 1 mode 3 single-chip mode 12 table 1-3. pin functions (3) pin no. dc-64s type symbol dp-64s fp-64a cp-68 i/o name and function serial com- txd 9 1 10 o transmit data: data output pin for the munication serial communication interface. interface rxd 10 2 11 i receive data: data input pin for the serial communication interface. sck 11 3 12 i/o serial clock: input/output pin for the serial clock. 16-bit free- ftoa, 32, 24, 34, o frt output compare a and b: output running ftob 37 29 40 pins controlled by comparators a and b timer of the free-running timer. ftci 31 23 33 i frt counter clock input: input pin for an external clock signal for the free-running timer. ftia to 33 to 36 25 to 28 36 to 39 i frt input capture a to d: input capture ftid pins for the free-running timer. 8-bit tmo 0 , 35, 27, 38, o 8-bit timer output: compare-match timer tmo 1 38 30 41 output pins for the 8-bit timers. tmci 0 , 31, 23, 33, i 8-bit timer counter clock input: tmci 1 36 28 39 external clock input pins for the 8-bit timer counters. tmri 0 , 34, 26, 37, i 8-bit timer counter reset input: tmri 1 37 29 40 a high input at these pins resets the 8-bit timer counters. a/d an 7 to an 0 22 to 29 14 to 21 24 to 31 i analog input: analog signal input pins converter for the a/d converter. adtrg 1 57 2 i a/d trigger: external trigger input for starting the a/d converter. av cc 30 22 32 i analog reference voltage: reference voltage pin for the a/d converter. if the a/d converter is not used, connect av cc to the system power supply (+5v). av ss 21 13 23 i analog ground: ground pin for the a/d converter. 13 table 1-3. pin functions (4) pin no. dc-64s type symbol dp-64s fp-64a cp-68 i/o name and function general- p1 7 to p1 0 49 to 56 41 to 48 53 to 60 i/o port 1: an 8-bit input/output port with purpose programmable mos input pull-ups and i/o led driving capability. the direction of each bit can be selected in the port 1 data direction register (p1ddr). p2 7 to p2 0 40 to 47 32 to 39 43 to 50 i/o port 2: an 8-bit input/output port with programmable mos input pull-ups and led driving capability. the direction of each bit can be selected in the port 2 data direction register (p2ddr). p3 7 to p3 0 57 to 64 49 to 56 61 to 68 i/o port 3: an 8-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 3 data direction register (p3ddr). p4 7 to p4 0 1 to 8 57 to 64 2 to 9 i/o port 4: an 8-bit input/output port. the direction of each bit can be selected in the port 4 data direction register (p4ddr). p5 2 to p5 0 9 to 11 1 to 3 10 to 12 i/o port 5: a 3-bit input/output port. the direction of each bit can be selected in the port 5 data direction register (p5ddr). p6 7 to p6 0 31 to 38 23 to 30 33, 34, i/o port 6: an 8-bit input/output port. the 36 to 41 direction of each bit can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 0 22 to 29 14 to 21 24 to 31 i port 7: an 8-bit input port. 14 section 2. mcu operating modes and address space 2.1 overview 2.1.1 mode selection the h8/329 series operates in three modes numbered 1, 2, and 3. the mode is selected by the inputs at the mode pins (md 1 and md 0 ) when the chip comes out of a reset. see table 2-1. the romless versions (hd6413298 and hd6413278) can be used only in mode 1 (expanded mode with on-chip rom disabled.) table 2-1. operating modes mode md 1 md 0 address space on-chip rom on-chip ram mode 0 low low mode 1 low high expanded disabled enabled* mode 2 high low expanded enabled enabled* mode 3 high high single-chip enabled enabled note: * if the rame bit in the system control register (syscr) is cleared to 0, off-chip memory can be accessed instead. modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices. the maximum address space supported by these externally expanded modes is 64k bytes. in mode 3 (single-chip mode), only on-chip rom and ram and the on-chip register field are used. all ports are available for general-purpose input and output. mode 0 is inoperative in the h8/329 series. avoid setting the mode pins to mode 0. 15 2.1.2 mode and system control registers (mdcr and syscr) table 2-2 lists the registers related to the operating mode: the system control register (syscr) and mode control register (mdcr). the mode control register indicates the inputs to the mode pins md 1 and md 0 . table 2-2. mode and system control registers name abbreviation read/write address system control register syscr r/w h'ffc4 mode control register mdcr r h'ffc5 2.2 system control register (syscr)?'ffc4 bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg rame initial value 0 0 0 0 1 0 1 1 read/write r/w r/w r/w r/w r/w r/w the system control register (syscr) is an 8-bit register that controls the operation of the chip. bit 7?oftware standby (ssby): enables transition to the software standby mode. for details, see section 12, ?ower-down state. on recovery from software standby mode by an external interrupt, the ssby bit remains set to ?. it can be cleared by writing ?. bit 7 ssby description 0 the sleep instruction causes a transition to sleep mode. (initial value) 1 the sleep instruction causes a transition to software standby mode. 16 bits 6 to 4?tandby timer select 2 to 0 (sts2 to sts0): these bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. during the selected time the cpu and on-chip supporting modules continue to stand by. these bits should be set according to the clock frequency so that the settling time is at least 10ms. for specific settings, see section 12.2, ?ystem control register: power-down control bits. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 settling time = 8192 states (initial value) 0 0 1 settling time = 16384 states 0 1 0 settling time = 32768 states 0 1 1 settling time = 65536 states 1 settling time = 131072 states bit 3?eserved: this bit cannot be modified and is always read as ?. bit 2?mi edge (nmieg): selects the valid edge of the nmi input. bit 2 nmieg description 0 an interrupt is requested on the falling edge of the nmi input. (initial value) 1 an interrupt is requested on the rising edge of the nmi input. bit 1?eserved: this bit cannot be modified and is always read as ?. bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized by a reset, but is not initialized in the software standby mode. bit 0 rame description 0 the on-chip ram is disabled. 1 the on-chip ram is enabled. (initial value) 17 2.3 mode control register (mdcr)?'ffc5 bit 7 6 5 4 3 2 1 0 mds1 mds0 initial value 1 1 1 0 0 1 * * read/write r r note: * initialized according to md 1 and md 0 inputs. the mode control register (mdcr) is an eight-bit register that indicates the operating mode of the chip. bits 7 to 5?eserved: these bits cannot be modified and are always read as ?. bits 4 and 3?eserved: these bits cannot be modified and are always read as ?. bit 2?eserved: this bit cannot be modified and is always read as ?. bits 1 and 0?ode select 1 and 0 (mds1 and mds0): these bits indicate the values of the mode pins (md 1 and md 0 ), thus indicating the current operating mode of the chip. mds1 corresponds to md 1 and mds0 to md 0 . these bits can be read but not written. when the mode control register is read, the levels at the mode pins (md 1 and md 0 ) are latched in these bits. 18 2.4 address space maps figures 2-1 to 2-4 show memory maps of the h8/329, h8/328, h8/327, and h8/326 in modes 1, 2, and 3. figure 2-1. h8/329 address space map h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'0048 h'0047 h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'ffff h'ff88 h'ff7f h'fb80 h'8000 h'7fff h'0048 h'0047 h'0000 h'0048 h'0047 h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 32k bytes vector table vector table external address space on-chip ram , 1k byte on-chip ram, 1k byte external address space external address space external address space on-chip ram , * 1k byte on-chip register field on-chip register field on-chip register field external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. note: * h'7fff on-chip rom, 32k bytes * h8/329 u.m. '92 fig. 3-1 19 figure 2-2. h8/328 address space map h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'0048 h'0047 h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'ffff h'ff88 h'ff7f h'fb80 h'8000 h'7fff h'6000 h'5fff h'0048 h'0047 h'0000 h'0048 h'0047 h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 24k bytes vector table vector table reserved * 1 external address space on-chip ram * 2 , 1k byte on-chip ram, 1k byte external address space external address space external address space on-chip ram * 2 , 1k byte on-chip register field on-chip register field on-chip register field do not access these reserved areas. external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. notes: * 1 * 2 h'5fff on-chip rom, 24k bytes h8/329 u.m. '92 fig. 3-2 20 figure 2-3. h8/327 address space map h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fd80 h'fd7f h'fb80 h'fb7f h'0048 h'0047 h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fd80 h'fd7f h'fb80 h'fb7f h'ffff h'ff88 h'ff7f h'fd80 h'8000 h'7fff h'4000 h'3fff h'0048 h'0047 h'0000 h'0048 h'0047 h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 16k bytes vector table vector table reserved * 1 reserved * 1, * 2 reserved * 1, * 2 external address space on-chip ram * 2 , 512 bytes on-chip ram, 512 bytes external address space external address space external address space on-chip ram * 2 , 512 bytes on-chip register field on-chip register field on-chip register field do not access these reserved areas. external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. notes: * 1 * 2 h'3fff on-chip rom, 16k bytes h8/329 u.m. '92 fig. 3-3 21 figure 2-4. h8/326 address space map h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fe80 h'fe7f h'fb80 h'fb7f h'0048 h'0047 h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fe80 h'fe7f h'fb80 h'fb7f h'ffff h'ff88 h'ff7f h'fe80 h'8000 h'7fff h'2000 h'1fff h'0048 h'0047 h'0000 h'0048 h'0047 h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 8k bytes vector table vector table reserved * 1 reserved * 1, * 2 reserved * 1, * 2 external address space on-chip ram * 2 , 256 bytes on-chip ram, 256 bytes external address space external address space external address space on-chip ram * 2 , 256 bytes on-chip register field on-chip register field on-chip register field do not access these reserved areas. external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. notes: * 1 * 2 h'1fff on-chip rom, 8k bytes h8/329 u.m. '92 fig. 2-4 22 section 3. cpu 3.1 overview the h8/329 series has the h8/300 cpu: a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high- speed operation. 3.1.1 features the main features of the h8/300 cpu are listed below. two-way register configuration sixteen 8-bit general registers, or eight 16-bit general registers instruction set with 57 basic instructions, including: multiply and divide instructions powerful bit-manipulation instructions eight addressing modes register direct (rn) register indirect (@rn) register indirect with displacement (@(d:16, rn)) register indirect with post-increment or pre-decrement (@rn+ or @?n) absolute address (@aa:8 or @aa:16) immediate (#xx:8 or #xx:16) pc-relative (@(d:8, pc)) memory indirect (@@aa:8) maximum 64k-byte address space high-speed operation all frequently-used instructions are executed two to four states the maximum clock rate is 10mhz 8- or 16-bit register-register add or subtract: 0.2 s 8 8-bit multiply: 1.4 s 16 8-bit divide: 1.4 s power-down mode sleep instruction 23 3.2 register configuration figure 3-1 shows the register structure of the cpu. there are two groups of registers: the general registers and control registers. figure 3-1. cpu registers 3.2.1 general registers all the general registers can be used as both data registers and address registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). when used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers (r0h to r7h and r0l to r7l). r7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. in assembly-language coding, r7 can also be denoted by the letters sp. as indicated in figure 3-2, r7 (sp) points to the top of the stack. 0 7 r0h r0l r1h r1l r2h r2l r3l r3h r4l r4h r5h r5l r6h r6l r7h r7l (sp) 0 15 pc 0 2 3 5 c v z h 0 7 ccr n i 1 7 sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag half-carry flag interrupt mask bit user bit negative flag u u user bit fig. 3-1 6 4 24 figure 3-2. stack pointer 3.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). (1) program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. each instruction is accessed in 16 bits (1 word), so the least significant bit of the pc is ignored (always regarded as 0). (2) condition code register (ccr): this 8-bit register contains internal status information, including carry (c), overflow (v), zero (z), negative (n), and half-carry (h) flags and the interrupt mask bit (i). bit 7?nterrupt mask bit (i): when this bit is set to ?,?all interrupts except nmi are masked. this bit is set to ??automatically by a reset and at the start of interrupt handling. bit 6?ser bit (u): this bit can be written and read by software (using the ldc, stc, andc, orc, and xorc instructions). bit 5?alf-carry flag (h): this flag is set to ??when the add.b, addx.b, sub.b, subx.b, neg.b, or cmp.b instruction causes a carry or borrow out of bit 3, and is cleared to ? otherwise. similarly, it is set to ??when the add.w, sub.w, or cmp.w instruction causes a carry or borrow out of bit 11, and cleared to ??otherwise. it is used implicitly in the daa and das instructions. bit 4?ser bit (u): this bit can be written and read by software (using the ldc, stc, andc, orc, and xorc instructions). sp unused area stack area (r7) fig. 3-2 25 bit 3?egative flag (n): this flag indicates the most significant bit (sign bit) of the result of an instruction. bit 2?ero flag (z): this flag is set to ??to indicate a zero result and cleared to ??to indicate a nonzero result. bit 1?verflow flag (v): this flag is set to ??when an arithmetic overflow occurs, and cleared to ??at other times. bit 0?arry flag (c): this flag is used by: add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result shift and rotate instructions, to store the value shifted out of the most significant or least significant bit bit manipulation and bit load instructions, as a bit accumulator the ldc, stc, andc, orc, and xorc instructions enable the cpu to load and store the ccr, and to set or clear selected bits by logic operations. the n, z, v, and c flags are used in conditional branching instructions (b cc ). for the action of each instruction on the flag bits, see the h8/300 series programming manual . 3.2.3 initial register values when the cpu is reset, the program counter (pc) is loaded from the vector table and the interrupt mask bit (i) in the ccr is set to ?.? the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. to prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 26 3.3 addressing modes 3.3.1 addressing mode the h8/300 cpu supports eight addressing modes. each instruction uses a subset of these addressing modes. table 3-1. addressing modes no. addressing mode symbol (1) register direct rn (2) register indirect @rn (3) register indirect with displacement @(d:16, rn) (4) register indirect with post-increment @rn+ register indirect with pre-decrement @?n (5) absolute address @aa:8 or @aa:16 (6) immediate #xx:8 or #xx:16 (7) program-counter-relative @(d:8, pc) (8) memory indirect @@aa:8 (1) register direct?n: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. in most cases the general register is accessed as an 8-bit register. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. (2) register indirect?rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) register indirect with displacement?(d:16, rn): this mode, which is used only in mov instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. for the mov.w instruction, the resulting address must be even. (4) register indirect with post-increment or pre-decrement?rn+ or @?n: register indirect with post-increment?rn+ the @rn+ mode is used with mov instructions that load registers from memory. it is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. the size of the increment is 27 1 or 2 depending on the size of the operand: 1 for mov.b; 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. register indirect with pre-decrement??n the @?n mode is used with mov instructions that store register contents to memory. it is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. the size of the decrement is 1 or 2 depending on the size of the operand: 1 for mov.b; 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. (5) absolute address?aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the mov.b instruction uses an 8-bit absolute address of the form h'ffxx. the upper 8 bits are assumed to be 1, so the possible address range is h'ff00 to h'ffff (65280 to 65535). the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. (6) immediate?xx:8 or #xx:16: the instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) program-counter-relative?(d:8, pc): this mode is used to generate branch addresses in the bcc and bsr instructions. an 8-bit value in byte 2 of the instruction code is added as a sign- extended value to the program counter contents. the result must be an even number. the possible branching range is ?26 to +128 bytes (?3 to +64 words) from the current address. (8) memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address from h'0000 to h'00ff (0 to 255). the word located at this address contains the branch address. note that addresses h'0000 to h'0047 (0 to 71) are located in the vector table. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as ?,?causing word access to be performed at the address preceding the specified address. see section 3.4.2, ?emory data formats,?for further information. 28 3.3.2 how to calculate where the execution starts table 3-2 shows how to calculate the effective address (ea: effective address) for each addressing mode. in the operation instruction, 1) register direct, as well as 6) immediate (for each instruction, add.b, addx, subx, cmp.b, and, or, xor) are used. in the move instruction, 7) program counter relative and 8) all addressing mode to delete the memory indirect can be used. in the bit manipulation instruction for the operand specifications, 1) register direct, 2) register indirect, as well as 5) absolute address (8 bit) can be used. furthermore, to specify the bit number within the operand, 1) register direct (for each instruction, bset, bclr, bnot, btst) as well as 6) immediate (3 bit) can be used independently. 29 table 3-2. effective address calculation (1) addressing mode and instruction format op reg 7 6 3 4 0 15 no. effective address calculation effective address 1 register direct, rn operands are contained in registers regm and regn register indirect, @rn 16-bit register contents 0 15 register indirect with displacement, @(d:16, rn) op regm regn 8 7 3 4 0 15 op reg 7 6 3 4 0 15 disp op reg 7 6 3 4 0 15 register indirect with post-increment, @rn+ op reg 7 6 3 4 0 15 register indirect with pre-decrement, @ern 2 3 4 1 for a byte operand, 2 for a word operand 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 regm 3 0 regn 3 0 16-bit register contents 16-bit register contents 16-bit register contents * * * note: 30 table 3-2. effective address calculation (2) addressing mode and instruction format no. effective address calculation effective address 5 absolute address @aa:8 operand is 1- or 2-byte immediate data @aa:16 op 8 7 0 15 op 0 15 imm op disp 7 0 15 pc-relative @(d:8, pc) 6 7 0 15 pc contents 0 15 0 15 abs h'ff 8 7 0 15 0 15 abs op #xx:16 op 8 7 0 15 imm immediate #xx:8 8 sign extension disp 31 table 3-2. effective address calculation (3) addressing mode and instruction format no. effective address calculation effective address 8 memory indirect, @@aa:8 op 8 7 0 15 memory contents (16 bits) 0 15 abs h'00 8 7 0 15 notation reg: op: disp: imm: abs: general register operation code displacement immediate data absolute address 32 3.4 data formats the h8/300 cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. all arithmetic and logic instructions except adds and subs can operate on byte data. the daa and das instruction perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions operate on word data. 33 3.4.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 3-3. figure 3-3. register data formats note: rnh: upper digit of general register rnl: lower digit of general register msb: most significant bit lsb: least significant bit 4-bit bcd data 1-bit data 1-bit data byte data byte data word data 4-bit bcd data data type rnl rnh rnl rnh rnl rn rnh register no. don't-care 4 3 7 0 data format 7 0 7 6 5 4 3 2 1 0 don't-care don't-care 7 6 5 4 3 2 1 0 don't-care 7 0 don't-care 7 0 0 15 don't-care 4 3 7 0 7 0 m s b l s b m s b l s b upper digit lower digit upper digit lower digit m s b l s b 34 3.4.2 memory data formats figure 3-4 indicates the data formats in memory. word data stored in memory must always begin at an even address. in word access the least significant bit of the address is regarded as ?.? if an odd address is specified, no address error occurs but the access is performed at the preceding even address. this rule affects mov.w instructions and branching instructions, and implies that only even addresses should be stored in the vector table. figure 3-4. memory data formats when the stack is addressed using r7, it must always be accessed a word at a time. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are returned, the lower byte is ignored. 7 0 7 6 5 4 3 2 1 0 1-bit data byte data word data byte data (ccr) on stack word data on stack data type data format address address n address n even address odd address even address odd address even address odd address m s b l s b m s b l s b upper 8 bits lower 8 bits m s b m s b l s b l s b ccr ccr * m s b l s b ccr: condition code register note: * ignored when returned 35 3.5 instruction set table 3-3 lists the h8/300 instruction set. table 3-3. instruction classification notes: *1 push rn is equivalent to mov.w rn, @?p. pop rn is equivalent to mov.w @sp+, rn. *2 bcc is a conditional branch instruction in which cc represents a condition code. *3 not supported by the h8/329 series. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. function instructions types data transfer mov, movtpe *3 , movfpe *3 , push *1 , pop *1 3 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, 14 daa, das, mulxu, divxu, cmp, neg logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, 8 rotxr bit manipulation bset, bclr, bnot, btst, band, biand, bor, 14 bior, bxor, bixor, bld, bild, bst, bist branch bcc *2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total 57 36 operation notation rd general register (destination) rs general register (source) rn general register (ead) destination operand (eas) source operand sp stack pointer pc program counter ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr #imm immediate data #xx:3 3-bit immediate data #xx:8 8-bit immediate data #xx:16 16-bit immediate data disp displacement + addition subtraction multiplication division and logical or logical ? exclusive or logical ? move not 37 3.5.1 data transfer instructions table 3-4 describes the data transfer instructions. figure 3-5 shows their object code formats. table 3-4. data transfer instructions note: * size: operand size b: byte w: word instruction size* function mov b/w (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:8 or #xx:16, @?n, and @rn+ addressing modes are available for byte or word data. the @aa:8 addressing mode is available for byte data only. the @?7 and @r7+ modes require word operands. do not specify byte size for these two modes. movtpe b not supported by the h8/329 series. movfpe b not supported by the h8/329 series. push w rn ? @?p pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @?p. pop w @sp+ ? rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. 38 figure 3-5. data transfer instruction codes 15 8 7 0 mov r r rm ? rn rn ? @rm, or @rm ? rn @(d:16, rm) ? rn, or disp. rn ? @(d:16, rm) @rm+ ? rn, or rn ? @erm abs. @aa:8 ? rn, or rn ? @aa:8 @aa:16 ? rn, or abs. rn ? @aa:16 r #imm. #xx:8 ? rn #xx:16 ? rn #imm. r movfpe, movtpe abs. m n r r m n r n n r n n op op op op op op op op r n op push, pop r r m n r r m n r n op op: operation field r m , r n : register field disp.: displacement abs.: absolute address #imm.: immediate data 39 3.5.2 arithmetic operations table 3-5 describes the arithmetic instructions. see figure 3-6 in section 3.5.4, ?hift operations for their object codes. table 3-5. arithmetic instructions note: * size: operand size b: byte w: word instruction size* function add b/w rd rs ? rd, rd + #imm ? rd sub performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx b rd rs c ? rd, rd #imm c ? rd subx performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc b rd #1 ? rd dec increments or decrements a general register. adds w rd #imm ? rd subs adds or subtracts immediate data to or from data in a general register. the immediate data must be 1 or 2. daa b rd decimal adjust ? rd das decimal-adjusts (adjusts to packed bcd) an addition or subtraction result in a general register by referring to the ccr. mulxu b rd rs ? rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. divxu b rd rs ? rd performs 16-bit 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. cmp b/w rd ?rs, rd ?#imm compares data in a general register with data in another general register or with immediate data. word data can be compared only between two general registers. neg b 0 ?rd ? rd obtains the two s complement (arithmetic complement) of data in a general register. 40 3.5.3 logic operations table 3-6 describes the four instructions that perform logic operations. see figure 3-6 in section 3.5.4, ?hift operations,?for their object codes. table 3-6. logic operation instructions note: * size: operand size b: byte 3.5.4 shift operations table 3-7 describes the eight shift instructions. figure 3-6 shows the object code formats of the arithmetic, logic, and shift instructions. table 3-7. shift instructions note: * size: operand size b: byte instruction size* function and b rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b (rd) ? (rd) obtains the one s complement (logical complement) of general register contents. instruction size* function shal b rd shift ? rd shar performs an arithmetic shift operation on general register contents. shll b rd shift ? rd shlr performs a logical shift operation on general register contents. rotl b rd rotate ? rd rotr rotates general register contents. rotxl b rd rotate through carry ? rd rotxr rotates general register contents through the c (carry) bit. 41 figure 3-6. arithmetic, logic, and shift instruction codes 15 8 7 0 add, sub, cmp addx, subx (rm), mulxu, divxu op adds, subs, inc, dec, daa, das, neg, not op #imm. add, addx, subx, cmp (#xx:8) and, or, xor (rm) #imm. and, or, xor (#xx:8) shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op op op op r m r n r n r n r m r n r n r n op: operation field r m , r n : register field #imm.: immediate data 42 3.5.5 bit manipulations table 3-8 describes the bit-manipulation instructions. figure 3-7 shows their object code formats. table 3-8. bit-manipulation instructions (1) note: * size: operand size b: byte instruction size* function bset b 1 ? ( table 3-8. bit-manipulation instructions (2) note: * size: operand size b: byte notes on bit manipulation instructions: bset, bclr, bnot, bst, and bist are read-modify- write instructions. they read a byte of data, modify one bit in the byte, then write the byte back. care is required when these instructions are applied to registers with write-only bits and to the i/o port registers. example: bclr is executed to clear bit 0 in the port 4 data direction register (p4ddr) under the following conditions. p4 7 : input pin, low p4 6 : input pin, high p4 5 ?p4 0 : output pins, low the intended purpose of this bclr instruction is to switch p4 0 from output to input. instruction size* function bixor b c ? [( before execution of bclr instruction execution of bclr instruction bclr #0, @p4ddr ;clear bit 0 in data direction register after execution of bclr instruction explanation: to execute the bclr instruction, the cpu begins by reading p4ddr. since p4ddr is a write-only register, it is read as h'ff, even though its true value is h'3f. next the cpu clears bit 0 of the read data, changing the value to h'fe. finally, the cpu writes this value (h'fe) back to p4ddr to complete the bclr instruction. as a result, p4 0 ddr is cleared to ?,?making p4 0 an input pin. in addition, p4 7 ddr and p4 6 ddr are set to ?,?making p4 7 and p4 6 output pins. p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output pin state low high low low low low low low ddr 0 0 1 1 1 1 1 1 dr 1 0 0 0 0 0 0 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output output output output output output output output input pin state low high low low low low low high ddr 1 1 1 1 1 1 1 0 dr 1 0 0 0 0 0 0 0 45 figure 3-7. bit manipulation instruction codes 15 8 7 0 bset, bclr, bnot, btst #imm. operand: register direct (rn) bit no.: immediate (#xx:3) r n op r 0 0 0 0 operand: register indirect (@rn) #imm. 0 0 0 0 bit no.: immediate (#xx:3) n op op r 0 0 0 0 operand: register indirect (@rn) r 0 0 0 0 bit no.: register direct (rm) m n op op abs. operand: absolute (@aa:8) #imm. 0 0 0 0 bit no.: immediate (#xx:3) op op r 0 0 0 0 operand: register indirect (@rn) #imm. 0 0 0 0 bit no.: immediate (#xx:3) n op op abs. operand: absolute (@aa:8) #imm. 0 0 0 0 bit no.: immediate (#xx:3) op op r 0 0 0 0 operand: register indirect (@rn) #imm. 0 0 0 0 bit no.: immediate (#xx:3) n op op band, bor, bxor, bld, bst #imm. operand: register direct (rn) bit no.: immediate (#xx:3) r n op biand, bior, bixor, bild, bist #imm. operand: register direct (rn) bit no.: immediate (#xx:3) r n op abs. operand: absolute (@aa:8) 0 0 0 0 bit no.: immediate (#xx:3) #imm. op op operand: register direct (rn) bit no.: register direct (rm) op r n r m abs. operand: absolute (@aa:8) 0 0 0 0 bit no.: register direct (rm) op op r m op: operation field r m , r n : register field abs.: absolute address #imm.: immediate data 46 3.5.6 branching instructions table 3-9 describes the branching instructions. figure 3-8 shows their object code formats. table 3-9. branching instructions instruction size function bcc branches to the specified address if condition cc is true. mnemonic cc field description condition bra (bt) 0 0 0 0 always (true) always brn (bf) 0 0 0 1 never (false) never bhi 0 0 1 0 high c z = 0 bls 0 0 1 1 low or same c z = 1 bcc (bhs) 0 1 0 0 carry clear c = 0 (high or same) bcs (blo) 0 1 0 1 carry set (low) c = 1 bne 0 1 1 0 not equal z = 0 beq 0 1 1 1 equal z = 1 bvc 1 0 0 0 overflow clear v = 0 bvs 1 0 0 1 overflow set v = 1 bpl 1 0 1 0 plus n = 0 bmi 1 0 1 1 minus n = 1 bge 1 1 0 0 greater or equal n ? v = 0 blt 1 1 0 1 less than n ? v = 1 bgt 1 1 1 0 greater than z (n ? v) = 0 ble 1 1 1 1 less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address. jsr branches to a subroutine at a specified address. bsr branches to a subroutine at a specified displacement from the current address. rts returns from a subroutine 47 figure 3-8. branching instruction codes 15 8 7 0 cc disp. bcc 0 0 0 0 jmp (@rm) jmp (@aa:16) abs. abs. jmp (@@aa:8) disp. bsr r 0 0 0 0 jsr (@rm) jsr (@aa:16) abs. jsr (@@aa:8) rts m r m op op op op op op op op abs. op op: operation field cc: condition field r m : register field disp.: displacement abs.: absolute address 48 3.5.7 system control instructions table 3-10 describes the system control instructions. figure 3-9 shows their object code formats. table 3-10. system control instructions instruction size function rte returns from an exception-handling routine. sleep causes a transition to the power-down state. ldc b rs ? ccr, #imm ? ccr moves immediate data or general register contents to the condition code register. stc b ccr ? rd copies the condition code register to a specified general register. andc b ccr #imm ? ccr logically ands the condition code register with immediate data. orc b ccr #imm ? ccr logically ors the condition code register with immediate data. xorc b ccr ? #imm ? ccr logically exclusive-ors the condition code register with immediate data. nop pc + 2 ? pc only increments the program counter. note: * size: operand size b: byte 49 figure 3-9. system control instruction codes 3.5.8 block data transfer instruction table 3-11 describes the eepmov instruction. figure 3-10 shows its object code format. table 3-11. block data transfer instruction/eeprom write operation 15 8 7 0 rte, sleep, nop op r ldc, stc (rn) #imm. andc, orc, xorc, ldc (#xx:8) n op op op: operation field r n : register field #imm.: immediate data instruction size function eepmov if r4l 0 then repeat @r5+ ? @r6+ r4l ?1 ? r4l until r4l = 0 else next; moves a data block according to parameters set in general registers r4l, r5, and r6. r4l: size of block (bytes) r5: starting source address r6: starting destination address execution of the next instruction starts as soon as the block transfer is completed. 50 figure 3-10. block data transfer instruction/eeprom write operation code notes on eepmov instruction 1. the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. 2. when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. 3.6 cpu states the cpu has three states: the program execution state, exception-handling state, and power-down state. the power-down state is further divided into three modes: the sleep mode, software standby mode, and hardware standby mode. figure 3-11 summarizes these states, and figure 3-12 shows a map of the state transitions. figure 3-11. operating states 15 8 7 0 op op eeprom state program execution state the cpu executes successive program instructions. exception-handling state a transient state triggered by a reset or interrupt. the cpu executes a hardware sequence that includes loading the program counter from the vector table. power-down state sleep mode a state in which some or all of the chip software standby mode functions are stopped to conserve power. hardware standby mode r5 ? r5 + r4l ? ? r6 ? r6 + r4l h'ffff not allowed r5 ? r5 + r4l ? ? r6 ? r6 + r4l 51 op: operation field figure 3-12. state transitions 3.6.1 program execution state in this state the cpu executes program instructions. 3.6.2 exception-handling state the exception-handling state is a transient state that occurs when the cpu is reset or accepts an interrupt. in this state the cpu carries out a hardware-controlled sequence that prepares it to execute a user-coded exception-handling routine. in the hardware exception-handling sequence the cpu does the following: (1) saves the program counter and condition code register to the stack (except in the case of a reset). (2) sets the interrupt mask (i) bit in the condition code register to ?. (3) fetches the start address of the exception-handling routine from the vector table. (4) branches to that address, returning to the program execution state. see section 4, ?xception handling,?for further information on the exception-handling state. reset state hardware standby mode sleep instruction interrupt request res = 1 power-down state sleep mode exception - handling state program execution state software standby mode exception handling request exception handing sleep instruction with ssby bit set stby=1, res=0 nmi or irq 0 to irq 2 fig. 3-12 notes: * 1 a transition to the reset state occurs when res goes low, except when the chip is in the hardware standby mode. * 2 a transition from any state to the hardware standby mode occurs when stby goes low. 52 3.6.3 power-down state the power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. (1) sleep mode: the sleep mode is entered when a sleep instruction is executed. the cpu halts, but cpu register contents remain unchanged and the on-chip supporting modules continue to function. (2) software standby mode: the software standby mode is entered if the sleep instruction is executed while the ssby (software standby) bit in the system control register (syscr) is set. the cpu and all on-chip supporting modules halt. the on-chip supporting modules are initialized, but the contents of the on-chip ram and cpu registers remain unchanged. i/o port outputs also remain unchanged. (3) hardware standby mode: the hardware standby mode is entered when the input at the stby pin goes low. all chip functions halt, including i/o port output. the on-chip supporting modules are initialized, but on-chip ram contents are held. see section 12, ?ower-down state,?for further information. 3.7 access timing and bus cycle the cpu is driven by the system clock ( ). the period from one rising edge of the system clock to the next is referred to as a ?tate. memory access is performed in a two- or three-state bus cycle. on-chip memory, on-chip supporting modules, and external devices are accessed in different bus cycles as described below. 3.7.1 access to on-chip memory (ram and rom) on-chip rom and ram are accessed in a cycle of two states designated t 1 and t 2 . either byte or word data can be accessed, via a 16-bit data bus. figure 3-13 shows the on-chip memory access cycle. figure 3-14 shows the associated pin states. 53 figure 3-13. on-chip memory access cycle figure 3-14. pin states during on-chip memory access cycle bus cycle t1 state t2 state internal address bus address write data internal read signal internal data bus (read) read data internal write signal internal data bus (write) t2 state bus cycle t1 state address bus address data bus: high impedance state as: high rd: high wr: high 54 3.7.2 access to on-chip register field and external devices the on-chip register field (i/o ports, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: t 1 , t 2 , and t 3 . only one byte of data can be accessed per cycle, via an 8-bit data bus. access to word data or instruction codes requires two consecutive cycles (six states). figure 3-15 shows the access cycle for the on-chip register field. figure 3-16 shows the associated pin states. figures 3-17 (a) and (b) show the read and write access timing for external devices. figure 3-15. on-chip register field access cycle write data bus cycle t1 state t2 state t3 state internal address bus address internal read signal internal data bus (read) read data internal write signal internal data bus (write) 55 figure 3-16. pin states during on-chip register field access cycle figure 3-17 (a). external device access timing (read) bus cycle t1 state t2 state t3 state address bus address as: high rd: high wr: high data bus: high impedance state read cycle t1 state t2 state t3 state address bus address read data as rd wr: high data bus 56 figure 3-17 (b). external device access timing (write) write cycle t1 state t2 state t3 state address bus address write data as rd: high wr data bus 57 section 4. exception handling 4.1 overview the h8/329 series recognizes only two kinds of exceptions: interrupts and the reset. table 4-1 indicates their priority and the timing of their hardware exception-handling sequences. table 4-1. hardware exception-handling sequences and priority type of priority exception timing of exception-handling sequence high reset the hardware exception-handling sequence begins as soon as res changes from low to high. interrupt when an interrupt is requested, the hardware exception-handling sequence begins at the end of the current instruction, or at the end of low the current hardware exception-handling sequence. 4.2 reset 4.2.1 overview a reset has the highest exception-handling priority. when the res pin goes low, all current processing stops and the chip enters the reset state. the internal state of the cpu and the registers of the on-chip supporting modules are initialized. when res returns from low to high, the reset exception-handling sequence starts. 4.2.2 reset sequence the reset state begins when res goes low. to ensure correct resetting, at power-on the res pin should be held low for at least 20ms. in a reset during operation, the res pin should be held low for at least 10 system clock cycles. for the pin states during a reset, see appendix c, ?in states. when res returns from low to high, hardware carries out the following reset exception-handling sequence. 59 (1) the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit in the condition code register (ccr) is set to ?. (2) the cpu loads the program counter with the first word in the vector table (stored at addresses h'0000 and h'0001) and starts program execution. the res pin should be held low when power is switched off, as well as when power is switched on. figure 4-1 indicates the timing of the reset sequence in modes 2 and 3. figure 4-2 indicates the timing in mode 1. figure 4-1. reset sequence (mode 2 or 3, program stored in on-chip rom) (1) (2) (3) res (2) internal address bus internal read signal internal write signal internal data bus (16 bits) (1) reset vector address (h'0000) (2) starting address of program (contents of h'0000?'0001) (3) first instruction of program vector fetch internal processing instruction prefetch figure. 4-1 60 (1) (2) (3) (4) (5) (6) (7) (8) (1),(3) reset vector address: (1)=h'0000, (3)=h'0001 (2),(4) starting address of program (contents of reset vector): (2)=upper byte, (4)=lower byte (5),(7) starting address of program: (5)=(2)(4), (7)=(2)(4)+1 (6),(8) first instruction of program: (6)=first byte, (8)=second byte vector fetch internal process- ing instruction prefetch res d 7 to d 0 (8 bits) a 15 to a 0 rd wr figure. 4-2 figure 4-2. reset sequence (mode 1) 61 4.2.3 disabling of interrupts after reset after a reset, if an interrupt were to be accepted before initialization of the stack pointer (sp: r7), the program counter and condition code register might not be saved correctly, leading to a program crash. to prevent this, all interrupts, including nmi, are disabled immediately after a reset. the first program instruction is therefore always executed. this instruction should initialize the stack pointer (example: mov.w #xx:16, sp). 4.3 interrupts 4.3.1 overview the interrupt sources include four input pins for external interrupts (nmi, irq 0 to irq 2 ) and 18 internal sources in the on-chip supporting modules. table 4-2 lists the interrupt sources in priority order and gives their vector addresses. when two or more interrupts are requested, the interrupt with highest priority is served first. the features of these interrupts are: nmi has the highest priority and is always accepted. all internal and external interrupts except nmi can be masked by the i bit in the ccr. when the i bit is set to ?,?interrupts other than nmi are not accepted. irq 0 to irq 2 can be sensed on the falling edge of the input signal, or level-sensed. the type of sensing can be selected for each interrupt individually. nmi is edge-sensed, and either the rising or falling edge can be selected. all interrupts are individually vectored. the software interrupt-handling routine does not have to determine what type of interrupt has occurred. 62 table 4-2. interrupts address of entry interrupt source no. in vector table priority nmi 3 h'0006 h'0007 high irq 0 4 h'0008 h'0009 irq 1 5 h'000a h'000b irq 2 6 h'000c h'000d reserved 7 h'000e h'000f 8 h'0010 h'0011 9 h'0012 h'0013 10 h'0014 h'0015 11 h'0016 h'0017 16-bit free- icia (input capture a) 12 h'0018 h'0019 running timer icib (input capture b) 13 h'001a h'001b icic (input capture c) 14 h'001c h'001d icid (input capture d) 15 h'001e h'001f ocia (output compare a) 16 h'0020 h'0021 ocib (output compare b) 17 h'0022 h'0023 fovi (overflow) 18 h'0024 h'0025 8-bit timer 0 cmi0a (compare-match a) 19 h'0026 h'0027 cmi0b (compare-match b) 20 h'0028 h'0029 ovi0 (overflow) 21 h'002a h'002b 8-bit timer 1 cmi1a (compare-match a) 22 h'002c h'002d cmi1b (compare-match b) 23 h'002e h'002f ovi1 (overflow) 24 h'0030 h'0031 reserved 25 h'0032 h'0033 26 h'0034 h'0035 serial eri (receive error) 27 h'0036 h'0037 communication rxi (receive end) 28 h'0038 h'0039 interface txi (tdr empty) 29 h'003a h'003b tei (tsr empty) 30 h'003c h'003d reserved 31 h'003e h'003f 32 h'0040 h'0041 33 h'0042 h'0043 34 h'0044 h'0045 a/d converter adi (conversion end) 35 h'0046 h'0047 low notes: 1. h'0000 and h'0001 contain the reset vector. 2. h'0002 to h'0005 are reserved in the h8/329 series and are not available to the user. 63 4.3.2 interrupt-related registers the interrupt-related registers are the system control register (syscr), irq sense control register (iscr), and irq enable register (ier). table 4-3. registers read by interrupt controller name abbreviation read/write address system control register syscr r/w h'ffc4 irq sense control register iscr r/w h'ffc6 irq enable register ier r/w h'ffc7 system control register (syscr)?'ffc4 bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg rame initial value 0 0 0 0 1 0 1 1 read/write r/w r/w r/w r/w r/w r/w the valid edge on the nmi line is controlled by bit 2 (nmieg) in the system control register. bit 2?mi edge (nmieg): determines whether a nonmaskable interrupt is generated on the falling or rising edge of the nmi input signal. bit 2 nmieg description 0 an interrupt is generated on the falling edge of nmi. (initial state) 1 an interrupt is generated on the rising edge of nmi. see section 2.2, ?ystem control register,?for information on the other syscr bits. irq sense control register (iscr)?'ffc6 bit 7 6 5 4 3 2 1 0 irq 2 sc irq 1 sc irq 0 sc initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w bits 3 to 7?eserved: these bits cannot be modified and are always read as ?. 64 bits 0 to 2?rq 0 to irq 2 sense control (irq 0 sc to irq 2 sc): these bits determine whether irq 0 to irq 2 are level-sensed or sensed on the falling edge. bits 0 to 2 irq 0 sc to irq 2 sc description 0 an interrupt is generated when irq 0 to irq 2 (initial state) inputs are low. 1 an interrupt is generated by the falling edge of the irq 0 to irq 2 inputs. irq enable register (ier)?'ffc7 bit 7 6 5 4 3 2 1 0 irq 2 e irq 1 e irq 0 e initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w bits 3 to 7?eserved: these bits cannot be modified and are always read as ?. bits 0 to 2?rq 0 to irq 2 enable (irq 0 e to irq 2 e): these bits enable or disable the irq 0 to irq 2 interrupts individually. bits 0 to 2 irq 0 e to irq 2 e description 0 irq 0 to irq 2 interrupt requests are disabled. (initial state) 1 irq 0 to irq 2 interrupt requests are enabled. when edge sensing is selected (by setting bits irq 0 sc to irq 7 sc to ??, it is possible for an interrupt-handling routine to be executed even though the corresponding enable bit (irq 0 e to irq 7 e) is cleared to ??and the interrupt is disabled. if an interrupt is requested while the enable bit (irq 0 e to irq 7 e) is set to ?,?the request will be held pending until served. if the enable bit is cleared to ??while the request is still pending, the request will remain pending, although new requests will not be recognized. if the interrupt mask bit (i) in the ccr is cleared to ?,?the interrupt-handling routine can be executed even though the enable bit is now ?. 65 if execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. set the i bit to ??in the ccr, masking interrupts. note that the i bit is set to 1 automatically when execution jumps to an interrupt vector. 2. clear the desired bits from irq 0 e to irq 7 e to ??to disable new interrupt requests. 3. clear the corresponding irq 0 sc to irq 7 sc bits to ?,?then set them to ??again. pending irq n interrupt requests are cleared when i = ??in the ccr, irq n sc = ?,?and irq n e = ?. 4.3.3 external interrupts the external interrupts are nmi and irq 0 to irq 2 . these four interrupts can be used to recover from software standby mode. (1) nmi: a nonmaskable interrupt is generated on the rising or falling edge of the nmi input signal regardless of whether the i (interrupt mask) bit is set in the ccr. the valid edge is selected by the nmieg bit in the system control register. the nmi vector number is 3. in the nmi hardware exception-handling sequence the i bit in the ccr is set to ?. (2) irq 0 to irq 2 : these interrupt signals are level-sensed or sensed on the falling edge of the input, as selected by iscr bits irq 0 sc to irq 2 sc. these interrupts can be masked collectively by the i bit in the ccr, and can be enabled and disabled individually by setting and clearing bits irq 0 e to irq 2 e in the irq enable register. when one of these interrupts is accepted, the i bit is set to ?.? irq 0 to irq 2 have interrupt vector numbers 4 to 6. they are prioritized in order from irq 2 (low) to irq 0 (high). for details, see table 4-2. interrupts irq 0 to irq 2 do not depend on whether pins irq 0 to irq 2 are input or output pins. when using external interrupts irq 0 to irq 2 , clear the corresponding ddr bits to ??to set these pins to the input state, and do not use these pins for input to the a/d converter. 66 4.3.4 internal interrupts eighteen internal interrupts can be requested by the on-chip supporting modules. each interrupt source has its own vector number, so the interrupt-handling routine does not have to determine which interrupt has occurred. all internal interrupts are masked when the i bit in the ccr is set to ?.? when one of these interrupts is accepted, the i bit is set to 1 to mask further interrupts (except nmi). the vector numbers are 12 to 35. for the priority order, see table 4-2. 4.3.5 interrupt handling interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the cpu to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. figure 4-3 shows a block diagram of the interrupt controller. figure 4-3. block diagram of interrupt controller h161 h8/337 h.m '91 fig. 4-3 irq flag 0 irq 0 e adf adie cpu i (ccr) nmi interrupt interrupt controller priority decision irq 0 interrupt interrupt request vector number adi interrupt * note: * irq edge 0 irq 0 e irq flag 0 s q irq interrupt 0 for edge-sensed interrupts, these and gates change to the circuit shown below. 67 the irq interrupts and interrupts from the on-chip supporting modules all have corresponding enable bits. when the enable bit is cleared to ?,?the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. these interrupts can also all be masked by setting the cpu s interrupt mask bit (i) to ?.? accordingly, these interrupts are accepted only when their enable bit is set to ??and the i bit is cleared to ?. the nonmaskable interrupt (nmi) is always accepted, except in the reset state and hardware standby mode. when an nmi or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the cpu and indicates the corresponding vector number. (when two or more interrupts are requested, the interrupt controller selects the vector number of the interrupt with the highest priority.) when notified of an interrupt request, at the end of the current instruction or current hardware exception-handling sequence, the cpu starts the hardware exception-handling sequence for the interrupt and latches the vector number. figure 4-4 is a flowchart of the interrupt (and reset) operations. figure 4-6 shows the interrupt timing sequence for the case in which the software interrupt-handling routine is in on-chip rom and the stack is in on-chip ram. (1) an interrupt request is sent to the interrupt controller when an nmi interrupt occurs, and when an interrupt occurs on an irq input line or in an on-chip supporting module provided the enable bit of that interrupt is set to ?. (2) the interrupt controller checks the i bit in the ccr and accepts the interrupt request if the i bit is cleared to ?.? if the i bit is set to ??only nmi requests are accepted; other interrupt requests remain pending. (3) among all accepted interrupt requests, the interrupt controller selects the request with the highest priority and passes it to the cpu. other interrupt requests remain pending. (4) when it receives the interrupt request, the cpu waits until completion of the current instruction or hardware exception-handling sequence, then starts the hardware exception-handling sequence for the interrupt and latches the interrupt vector number. (5) in the hardware exception-handling sequence, the cpu first pushes the pc and ccr onto the stack. see figure 4-5. the stacked pc indicates the address of the first instruction that will be executed on return from the software interrupt-handling routine. (6) next the i bit in the ccr is set to ?,?masking all further interrupts except nmi. (7) the vector address corresponding to the vector number is generated, the vector table entry at this vector address is loaded into the program counter, and execution branches to the software interrupt-handling routine at the address indicated by that entry. 68 figure 4-4. hardware interrupt-handling sequence h161 h8/337 h.m '91 fig. 4-4 program execution no no no yes no yes yes yes no yes nmi? i = 0? irq 0 ? irq 1 ? adi? reset i ? 1 interrupt requested? pending latch vector no. save pc save ccr read vector address branch to software interrupt-handling routine yes 69 figure 4-5. usage of stack in interrupt handling sp(r7) sp-4 sp-3 sp-2 sp-1 sp(r7) stack area sp+1 sp+2 sp+3 sp+4 even address ccr ccr * pc (upper byte) pc (lower byte) before interrupt is accepted after interrupt is accepted pushed onto stack program counter condition code register stack pointer pc: ccr: sp: 1. 2. the pc contains the address of the first instruction executed after return. registers must be saved and restored by word access at an even address. notes: * ignored on return. figure. 4-5 70 figure 4-6. timing of interrupt sequence (3) (5) (6) (8) (9) (1) interrupt priority decision. wait for end of instruction. interrupt accepted internal process- ing stack vector fetch internal process- ing instruction fetch (first instruction of interrupt-handling routine) interrupt request signal internal address bus internal write signal internal read signal internal 16-bit data bus (1) instruction prefetch address (pushed on stack. instruction is executed on return from interrupt-handling routine.) (2) (4) instruction code (not executed) (3) instruction prefetch address (not executed) (5) sp? (6) sp? (7) ccr (8) address of vector table entry (9) vector table entry (address of first instruction interrupt-handling routine) (10) first instruction of interrupt-handling routine (1) (2) (4) (7) (9) (10) instruction fetch figure. 4-5 (1) instruction prefetch address (pushed on stack. instruction is executed on return from interrupt-handling routine.) (2) (4) instruction code (not executed) (3) instruction prefetch address (not executed) (5) sp? (6) sp? (7) ccr (8) address of vector table entry (9) vector table entry (address of first instruction of interrupt-handling routine) (10) first instruction of interrupt-handling routine 71 4.3.6 interrupt response time table 4-4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. since the h8/329 series accesses its on-chip memory 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip rom and the stack in on-chip ram. table 4-4. number of states before interrupt service number of states no. reason for wait on-chip memory external memory 1 interrupt priority decision 2 *3 2 *3 2 wait for completion of 1 to 13 5 to 17 *2 current instruction *1 3 save pc and ccr 4 12 *2 4 fetch vector 2 6 *2 5 fetch instruction 4 12 *2 6 internal processing 4 4 total 17 to 29 41 to 53 *2 notes: *1 these values do not apply if the current instruction is eepmov. *2 if wait states are inserted in external memory access, add the number of wait states. *3 1 for internal interrupts. 4.3.7 precaution note that the following type of contention can occur in interrupt handling. contention between interrupt request and disable: when software clears the enable bit of an interrupt to ??to disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. if an enable bit is cleared by a bclr or mov instruction, for example, and the interrupt is requested during execution of that instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution of the instruction, the hardware exception- handling sequence is executed for the interrupt. if a higher-priority interrupt is requested at the same time, however, the hardware exception-handling sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored. similar considerations apply when an interrupt request flag is cleared to ?. 72 figure 4-7 shows an example in which the ociae bit is cleared to ?. figure 4-7. contention between interrupt and disabling instruction the above contention does not occur if the enable bit or flag is cleared to ??while the interrupt mask bit (i) is set to ?. 4.4 note on stack handling in word access, the least significant bit of the address is always assumed to be 0. the stack is always accessed by word access. care should be taken to keep an even value in the stack pointer (general register r7). use the push and pop (or mov.w rn, @?p and mov.w @sp+, rn) instructions to push and pop registers on the stack. setting the stack pointer to an odd value can cause programs to crash. figure 4-8 shows an example of damage caused when the stack pointer contains an odd address. internal address bus ociae h161 h8/337 h.m '91 fig. 4-7 ocia interrupt handling ocia interrupt signal ocfa cpu write cycle to tier internal write signal tier address 73 figure 4-8. example of damage caused by setting an odd address in r7 although the ccr consists of only one byte, it is treated as word data when pushed on the stack. in the hardware interrupt exception-handling sequence, two identical ccr bytes are pushed onto the stack to make a complete word. when popped from the stack by an rte instruction, the ccr is loaded from the byte stored at the even address. the byte stored at the odd address is ignored. pc h r1 sp sp sp l pc l pc h'fecd h'fecf h'fecc bsr instruction mov.b r1l, @?7 pc is improperly stored beyond top of stack h'fecf set in sp pc is lost h pc : upper byte of program counter lower byte of program counter general register stack pointer pc : r1 : sp : h l l l figure. 4-7 74 section 5. i/o ports 5.1 overview the h8/329 series has seven parallel i/o ports, including: five 8-bit input/output ports?orts 1, 2, 3, 4, and 6 one 8-bit input port?ort 7 one 3-bit input/output port?ort 5 ports 1, 2, and 3 have programmable input pull-up transistors. ports 1 to 6 can drive a darlington pair. ports 1 to 4, and 6 can drive one ttl load and a 90pf capacitive load. port 5 can drive one ttl load and a 30pf capacitive load. ports 1 and 2 can drive leds (10ma current sink). input and output are memory-mapped. the cpu views each port as a data register (dr) located in the register field at the high end of the address space. each port (except port 7) also has a data direction register (ddr) which determines which pins are used for input and which for output. output: to send data to an output port, the cpu selects output in the data direction register and writes the desired data in the data register, causing the data to be held in a latch. the latch output drives the pin through a buffer amplifier. if the cpu reads the data register of an output port, it obtains the data held in the latch rather than the actual level of the pin. input: to read data from an i/o port, the cpu selects input in the data direction register and reads the data register. this causes the input logic level at the pin to be placed directly on the internal data bus. there is no intervening input latch. the data direction registers are write-only registers; their contents are invisible to the cpu. if the cpu reads a data direction register all bits are read as ?,?regardless of their true values. care is required if bit manipulation instructions are used to set and clear the data direction bits. see the note on bit manipulation instructions in section 3.5.5, ?it manipulations. auxiliary functions: in addition to their general-purpose input/output functions, all of the i/o ports have auxiliary functions. most of the auxiliary functions are software-selectable and must be enabled by setting bits in control registers. when selected, an auxiliary function usually replaces the general-purpose input/output function, but in some cases both functions can operate simultaneously. table 5-1 summarizes the functions of the ports. 75 table 5-1. port functions expanded modes single-chip mode port description pins mode 1 mode 2 mode 3 port 1 8-bit input-output p1 7 to p1 0 / address output general input general input/ port a 7 to a 0 (low) when ddr = ? output can drive leds (initial state) input pull-ups address output (low) when ddr = ? port 2 8-bit input-output p2 7 to p2 0 / address output general input general input/ port a 15 to a 8 (high) when ddr = ?? output can drive leds (initial state) input pull-ups address output (high) when ddr = ? port 3 8-bit input-output p3 7 to p3 0 / data bus data bus general input/ port d 7 to d 0 output input pull-ups port 4 8-bit input/output p4 7 /wait w ait input general input/ output p4 6 / system clock general input output when ddr = ?? (initial state) system clock output when ddr = ? p4 5 /as as output general input/ p4 4 /wr wr output output p4 3 /rd rd output p4 2 /irq 0 general input/output or external interrupt input p4 1 /irq 1 (irq 0 , irq 1 ) p4 0 /adtrg/ general input/output, a/d converter trigger input irq 2 (adtrg), or external interrupt input (irq 2 ) port 5 3-bit input-output p5 2 to p5 0 general input/output or serial communication interface port input/output (txd, rxd, sck) port 6 8-bit input-output p6 7 to p6 0 general input/output, 16-bit free-running timer port input/output (ftci, ft oa, ft ob, ftia, ftib, ftic, ftid), or 8-bit timer 0/1 input/output (tmci 0 , tmo 0 , tmri 0 , tmci 1 , tmo 1 , tmri 1 ) port 7 8-bit input port p7 7 to p7 0 general input, or analog input to a/d converter 76 5.2 port 1 port 1 is an 8-bit input/output port that also provides the low bits of the address bus. the function of port 1 depends on the mcu mode as indicated in table 5-2. table 5-2. functions of port 1 note: * depending on the bit settings in the data direction register: 0?nput pin; 1?ddress pin pins of port 1 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive light-emitting diodes and a darlington pair. when they are used as input pins, they have programmable mos transistor pull-ups. table 5-3 details the port 1 registers. table 5-3. port 1 registers port 1 data direction register (p1ddr)?'ffb0 mode 1 mode 2 mode 3 address bus (low) input port or input/output port (a 7 to a 0 ) address bus (low) (a 7 to a 0 )* name abbreviation read/write initial value address port 1 data direction register p1ddr w h'ff (mode 1) h'ffb0 h'00 (modes 2 and 3) port 1 data register p1dr r/w h'00 h'ffb2 port 1 input pull-up control p1pcr r/w h'00 h'ffac register bit 7 6 5 4 3 2 1 0 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 77 p1ddr is an 8-bit register that selects the direction of each pin in port 1. a pin functions as an output pin if the corresponding bit in p1ddr is set to ?,?and as an input pin if the bit is cleared to ?. port 1 data register (p1dr)?'ffb2 p1dr is an 8-bit register containing the data for pins p1 7 to p1 0 . when the cpu reads p1dr, for output pins it reads the value in the p1dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p1dr latch. port 1 input pull-up control register (p1pcr)?'ffac bit 7 6 5 4 3 2 1 0 p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p1pcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. if a bit in p1ddr is cleared to ??(designating input) and the corresponding bit in p1pcr is set to ?, the input pull-up transistor for that bit is turned on. mode 1: in mode 1 (expanded mode without on-chip rom), port 1 is automatically used for address output. the port 1 data direction register is unwritable. all bits in p1ddr are automatically set to ??and cannot be cleared to ?. mode 2: in mode 2 (expanded mode with on-chip rom), the usage of port 1 can be selected on a pin-by-pin basis. a pin is used for general-purpose input if its data direction bit is cleared to ?, or for address output if its data direction bit is set to ?. mode 3: in the single-chip mode port 1 is a general-purpose input/output port. bit 7 6 5 4 3 2 1 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 78 reset: a reset clears p1ddr, p1dr, and p1pcr to all ?,? placing all pins in the input state with the pull-up transistors off. in mode 1, when the chip comes out of reset, p1ddr is set to all ?. hardware standby mode: all pins are placed in the high-impedance state with the pull-up transistors off. p1dr and p1pcr are initialized to h'00. in modes 2 and 3, p1ddr is initialized to h'00. software standby mode: in the software standby mode, p1ddr, p1dr, and p1pcr remain in their previous state. address output pins are low. general-purpose output pins continue to output the data in p1dr. input pull-up transistors: port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 2 or 3, set the corresponding p1pcr bit to ??and clear the corresponding p1ddr bit to ?.?p1pcr is cleared to h'00 by a reset and in the hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. table 5-4 indicates the states of the input pull-up transistors in each operating mode. table 5-4. states of input pull-up transistors (port 1) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off on/off on/off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p1pcr = ??and p1ddr = ?,?but off otherwise. figure 5-1 shows a schematic diagram of port 1. 79 figure 5-1. port 1 schematic diagram 5.3 port 2 port 2 is an 8-bit input/output port that also provides the high bits of the address bus. the function of port 2 depends on the mcu mode as indicated in table 5-5. table 5-5. functions of port 2 mode 1 mode 2 mode 3 address bus (high) input port or input/output port (a 15 to a 8 ) address bus (high) (a 15 to a 8 )* note: * depending on the bit settings in the data direction register: 0?nput pin; 1?ddress pin h8/329 u.m. '92 fig. 5-1 p1 n hardware standby mode 3 mode 1 or 2 rp1 reset reset mode 1 reset wp1 wp1d wp1p r r s r q q q d d d p1 n dr p1 n ddr p1 n pcr c c c * rp1p internal address bus wp1p: wp1d: wp1: rp1p : rp1: n = 0 to 7 note: set-priority * write port 1 pcr write port 1 ddr write port 1 read port 1 pcr read port 1 internal data bus 80 pins of port 2 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive light-emitting diodes and a darlington pair. when they are used as input pins, they have programmable mos transistor pull-ups. table 5-6 details the port 2 registers. table 5-6. port 2 registers name abbreviation read/write initial value address port 2 data direction p2ddr w h'ff (mode 1) h'ffb1 register h'00 (modes 2 and 3) port 2 data register p2dr r/w h'00 h'ffb3 port 2 input pull-up p2pcr r/w h'00 h'ffad control register port 2 data direction register (p2ddr)?'ffb1 p2ddr is an 8-bit register that selects the direction of each pin in port 2. a pin functions as an output pin if the corresponding bit in p2ddr is set to ?,?and as an input pin if the bit is cleared to ?. port 2 data register (p2dr)?'ffb3 p2dr is an 8-bit register containing the data for pins p2 7 to p2 0 . when the cpu reads p2dr, for output pins it reads the value in the p2dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p2dr latch. bit 7 6 5 4 3 2 1 0 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 81 port 2 input pull-up control register (p2pcr)?'ffad bit 7 6 5 4 3 2 1 0 p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p2pcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. if a bit in p2ddr is cleared to ??(designating input) and the corresponding bit in p2pcr is set to ?, the input pull-up transistor for that bit is turned on. mode 1: in mode 1 (expanded mode without on-chip rom), port 2 is automatically used for address output. the port 2 data direction register is unwritable. all bits in p2ddr are automatically set to ??and cannot be cleared to ?. mode 2: in mode 2 (expanded mode with on-chip rom), the usage of port 2 can be selected on a pin-by-pin basis. a pin is used for general-purpose input if its data direction bit is cleared to ?, or for address output if its data direction bit is set to ?. mode 3: in the single-chip mode port 2 is a general-purpose input/output port. reset: a reset clears p2ddr, p2dr, and p2pcr to all ?,?placing all pins in the input state with the pull-up transistors off. in mode 1, when the chip comes out of reset, p2ddr is set to all ?. hardware standby mode: all pins are placed in the high-impedance state with the pull-up transistors off. p2dr and p2pcr are initialized to h'00. in modes 2 and 3, p2ddr is initialized to h'00. software standby mode: in the software standby mode, p2ddr, p2dr, and p2pcr remain in their previous state. address output pins are low. general-purpose output pins continue to output the data in p2dr. input pull-up transistors: port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 2 or 3, set the corresponding p2pcr bit to ??and clear the corresponding p2ddr bit to ?.? p2pcr is cleared to h'00 by a reset and in the hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. 82 table 5-7 indicates the states of the input pull-up transistors in each operating mode. table 5-7. states of input pull-up transistors (port 2) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off on/off on/off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p2pcr = ??and p2ddr = ?,?but off otherwise. figure 5-2 shows a schematic diagram of port 2. figure 5-2. port 2 schematic diagram h8/329 u.m. '92 fig. 5-2 p2 n hardware standby mode 3 mode 1 or 2 rp2 reset reset mode 1 reset wp2 wp2d wp2p r r s r q q q d d d p2 n dr p2n ddr p2 n pcr c c c * rp2p internal address bus wp2p: wp2d: wp2: rp2p : rp2: n = 0 to 7 note: set-priority * write port 2 pcr write port 2 ddr write port 2 read port 2 pcr read port 2 internal data bus 83 5.4 port 3 port 3 is an 8-bit input/output port that also provides the external data bus. the function of port 3 depends on the mcu mode as indicated in table 5-8. table 5-8. functions of port 3 mode 1 mode 2 mode 3 data bus data bus input/output port pins of port 3 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive a darlington pair. when they are used as input pins, they have program- mable mos transistor pull-ups. table 5-9 details the port 3 registers. table 5-9. port 3 registers name abbreviation read/write initial value address port 3 data direction register p3ddr w h'00 h'ffb4 port 3 data register p3dr r/w h'00 h'ffb6 port 3 input pull-up control p3pcr r/w h'00 h'ffae register port 3 data direction register (p3ddr)?'ffb4 p3ddr is an 8-bit register that selects the direction of each pin in port 3. a pin functions as an output pin if the corresponding bit in p3ddr is set to ?,?and as an input pin if the bit is cleared to ?. bit 7 6 5 4 3 2 1 0 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 84 port 3 data register (p3dr)?'ffb6 p3dr is an 8-bit register containing the data for pins p3 7 to p3 0 . when the cpu reads p3dr, for output pins it reads the value in the p3dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p3dr latch. port 3 input pull-up control register (p3pcr)?'ffae bit 7 6 5 4 3 2 1 0 p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p3pcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. if a bit in p3ddr is cleared to ??(designating input) and the corresponding bit in p3pcr is set to ?, the input pull-up transistor for that bit is turned on. modes 1 and 2: in the expanded modes, port 3 is automatically used as the data bus. the values in p3ddr, p3dr, and p3pcr are ignored. mode 3: in the single-chip mode, port 3 can be used as a general-purpose input/output port. bit 7 6 5 4 3 2 1 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 85 reset and hardware standby mode: a reset or entry to the hardware standby mode clears p3ddr, p3dr, and p3pcr to all ?.? all pins are placed in the high-impedance state with the pull-up transistors off. software standby mode: in the software standby mode, p3ddr, p3dr, and p3pcr remain in their previous state. in modes 1 and 2, all pins are placed in the data input (high-impedance) state. in mode 3, all pins remain in their previous input or output state. input pull-up transistors: port 3 has built-in programmable input pull-up transistors that are available in mode 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 3, set the corresponding p3pcr bit to ??and clear the corresponding p3ddr bit to ?.?p3pcr is cleared to h'00 by a reset and in the hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. table 5-10 indicates the states of the input pull-up transistors in each operating mode. table 5-10. states of input pull-up transistors (port 3) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off off off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p3pcr = ??and p3ddr = ?,?but off otherwise. figure 5-3 shows a schematic diagram of port 3. 86 figure 5-3. port 3 schematic diagram p3 n reset reset reset wp3 wp3d wp3p r r r q q q d d d p3 n dr p3 n ddr p3 n pcr c c c internal data bus rp3 h8/329 u.m. '92 fig. 5-3 external address write mode 1 or 2 external address read wp3p: wp3d: wp3: rp3p : rp3: n = 0 to 7 write port 3 pcr write port 3 ddr write port 3 read port 3 pcr read port 3 mode 3 mode 3 rp3p mode 3 87 5.5 port 4 port 4 is an 8-bit input/output port that also provides pins for interrupt input (irq 0 to irq 2 ), a/d trigger input, system clock ( ) output, and bus control signals (in the expanded modes). pins p4 7 to p4 3 have different functions in different modes. pins p4 2 to p4 0 have the same functions in all modes. table 5-11 lists the pin functions. table 5-11. port 4 pin functions pin expanded modes single-chip mode p4 0 p4 0 input/output , irq 2 input, and adtrg input (simultaneously) p4 1 p4 1 input/output and irq 1 input (simultaneously) p4 2 p4 2 input/output and irq 0 input (simultaneously) p4 3 rd output p4 3 input/output p4 4 wr output p4 4 input/output p4 5 as output p4 5 input/output p4 6 output p4 6 input or output p4 7 wait input p4 7 input/output pins of port 4 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. table 5-12 details the port 4 registers. table 5-12. port 4 registers name abbreviation read/write initial value address port 4 data direction register p4ddr w h'40 (modes 1 and 2) h'ffb5 h'00 (mode 3) port 4 data register p4dr r/w *1 undetermined *2 h'ffb7 notes: *1 bit 6 is read-only. *2 bit 6 is undetermined. other bits are initially ?. 88 port 4 data direction register (p4ddr)?'ffb5 p4ddr is an 8-bit register that selects the direction of each pin in port 4. a pin functions as an output pin if the corresponding bit in p4ddr is set to ?,?and as in input pin if the bit is cleared to ?. port 4 data register (p4dr)?'ffb7 note: * determined by the level at pin p4 6 . p4dr is an 8-bit register containing the data for pins p4 7 to p4 0 . when the cpu reads p4dr, for output pins (p4ddr = ?? it reads the value in the p4dr latch, but for input pins (p4ddr = ??, it obtains the logic level directly from the pin, bypassing the p4dr latch. this also applies to pins used for interrupt input, a/d trigger input, clock output, and control signal input or output. pins p4 0 , p4 1 , and p4 2 : can be used for general-purpose input or output, interrupt request input, or a/d trigger input. see table 5-11. if a pin is used for interrupt or a/d trigger input, its data direction bit should be cleared to ?,? so that the output from p4dr will not generate an interrupt request or a/d trigger signal. pins p4 3 , p4 4 and p4 5 : in modes 1 and 2 (the expanded modes), these pins are used for output of the rd, wr, and as bus control signals. they are unaffected by the values in p4ddr and p4dr. bit 7 6 5 4 3 2 1 0 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr modes 1 and 2 initial value 0 1 0 0 0 0 0 0 read/write w w w w w w w mode 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 initial value 0 * 0 0 0 0 0 0 read/write r/w r r/w r/w r/w r/w r/w r/w 89 in mode 3 (single-chip mode), these pins can be used for general-purpose input or output. pin p4 6 : in modes 1 and 2, this pin is used for system clock ( ) output. in mode 3, this pin is used for general-purpose input if p4 6 ddr is cleared to ?,?or system clock output if p4 6 ddr is set to ?. pin p4 7 : in modes 1 and 2, this pin is used for input of the wait bus control signal. it is unaffected by the values in p4ddr and p4dr. in mode 3 (single-chip mode), this pin can be used for general-purpose input or output. reset: in the single-chip mode (mode 3), a reset initializes all pins of port 4 to the general-purpose input function. in the expanded modes (modes 1 and 2), p4 0 to p4 2 are initialized as input port pins, and p4 3 to p4 7 are initialized to their bus control and system clock output functions. hardware standby mode: all pins are placed in the high-impedance state. 90 software standby mode: all pins remain in their previous state. for rd, wr, as, and this means the high output state. figures 5-4 to 5-8 show schematic diagrams of port 4. figure 5-4. port 4 schematic diagram (pin p4 0 ) h8/329 u.m. '92 fig. 5-4 p4 0 rp4 reset reset wp4 wp4d r r q q d d p4 0 dr p4. 0 ddr c c internal data bus wp4d: wp4: rp4: write port 4 ddr write port 4 read port 4 irq enable register irq 2 enable irq 2 input a/d converter module adtrg 91 figure 5-5. port 4 schematic diagram (pins p4 1 and p4 2 ) h8/329 u.m. '92 fig. 5-5 p4 n rp4 reset reset wp4 wp4d r r q q d d p4 n dr p4 n ddr c c wp4d: wp4: rp4: n = 1, 2 write port 4 ddr write port 4 read port 4 irq enable register irq 0 enable irq 1 enable irq 0 input irq 1 input internal data bus 92 figure 5-6. port 4 schematic diagram (pins p4 3 , p4 4 and p4 5 ) h8/329 u.m. '92 fig. 5-6 rp4 reset reset wp4 wp4d r r q q d d p4 n dr p4 n ddr c c wp4d: wp4: rp4: n = 3, 4, 5 write port 4 ddr write port 4 read port 4 rd output wr output as ouput p4 n internal data bus hardware standby mode 1 or 2 mode 3 mode 1 or 2 93 figure 5-7. port 4 schematic diagram (pin p4 6 ) h8/329 u.m. '92 fig. 5-7 p4 6 rp9 reset wp4d r q d p4 6 ddr c internal data bus wp4d: wp4: rp4: note: set-priority * write port 4 ddr write port 4 read port 4 hardware standby mode 1, 2 * s 94 figure 5-8. port 4 schematic diagram (pin p4 7 ) h8/329 u.m. '92 fig. 5-8 p4 7 rp4 reset reset wp4 wp4d r r q q d d p4 7 dr p4 7 ddr c c internal data bus wp4d: wp4: rp4: write port 4 ddr write port 4 read port 4 mode 1 or 2 wait input 95 5.6 port 5 port 5 is a 3-bit input/output port that also provides input and output pins for the serial communi- cation interface (sci). the pin functions depend on control bits in the serial control register (scr). pins not used for serial communication are available for general-purpose input/output. table 5-13 lists the pin functions, which are the same in both the expanded and single-chip modes. table 5-13. port 5 pin functions (modes 1 to 3) usage pin functions i/o port p5 0 p5 1 p5 2 serial communication interface txd rxd sck see section 8, ?erial communication interface?for details of the serial control bits. pins used by the serial communication interface are switched between input and output without regard to the values in the data direction register. pins of port 5 can drive a single ttl load and a 30pf capacitive load when they are used as output pins. they can also drive a darlington pair. table 5-14 details the port 5 registers. table 5-14. port 5 registers name abbreviation read/write initial value address port 5 data direction register p5ddr w h'f8 h'ffb8 port 5 data register p5dr r/w h'f8 h'ffba port 5 data direction register (p5ddr)?'ffb8 p5ddr is an 8-bit register that selects the direction of each pin in port 5. a pin functions as an output pin if the corresponding bit in p5ddr is set to ?,?and as an input pin if the bit is cleared to ?. bit 7 6 5 4 3 2 1 0 p5 2 ddr p5 1 ddr p5 0 ddr initial value 1 1 1 1 1 0 0 0 read/write w w w 96 port 5 data register (p5dr)?'ffba p5dr is an 8-bit register containing the data for pins p5 2 to p5 0 . when the cpu reads p5dr, for output pins (p5ddr = ?? it reads the value in the p5dr latch, but for input pins (p5ddr = ??, it obtains the logic level directly from the pin, bypassing the p5dr latch. this also applies to pins used for serial communication. pin p5 0 : this pin can be used for general-purpose input or output, or for output of serial transmit data (txd). when used for txd output, this pin is unaffected by the values in p5ddr and p5dr. pin p5 1 : this pin can be used for general-purpose input or output, or for input of serial receive data (rxd). when used for rxd input, this pin is unaffected by p5ddr and p5dr. pin p5 2 : this pin can be used for general-purpose input or output, or for serial clock input or output (sck). when used for sck input or output, this pin is unaffected by p5ddr and p5dr. reset and hardware standby mode: a reset or entry to the hardware standby mode makes all pins of port 5 into input port pins. software standby mode: in the software standby mode, the serial control register is initialized but p5ddr and p5dr remain in their previous states. all pins become input or output port pins depending on the setting of p5ddr. output pins output the values in p5dr. figures 5-9 to 5-11 show schematic diagrams of port 5. bit 7 6 5 4 3 2 1 0 p5 2 p5 1 p5 0 initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w 97 figure 5-9. port 5 schematic diagram (pin p5 0 ) h8/329 u.m. '92 fig. 5-9 rp5 reset reset wp5 wp5d r r q q d d p5 0 dr p5 0 ddr c c wp5d: wp5: rp5: write port 5 ddr write port 5 read port 5 sci module serial transmit enable serial transmit data p5 0 internal data bus 98 figure 5-10. port 5 schematic diagram (pin p5 1 ) h8/329 u.m. '92 fig. 5-10 p5 1 rp5 reset reset wp5 wp5d r r q q d d p5 1 dr p5 1 ddr c c internal data bus wp5d: wp5: rp5: write port 5 ddr write port 5 read port 5 sci module serial receive enable serial receive data 99 figure 5-11. port 5 schematic diagram (pin p5 2 ) h8/329 u.m. '92 fig. 5-11 rp5 reset reset wp5 wp5d r r q q d d p5 2 dr p5 2 ddr c c wp5d: wp5: rp5: write port 5 ddr write port 5 read port 5 sci module serial clock input enable serial clock output enble serial clock output enable serial clock input p5 2 internal data bus 100 5.7 port 6 port 6 is an 8-bit input/output port that also provides input and output pins for the 16-bit free- running timer and 8-bit timers. the pin functions depend on control bits in the control registers of the timers. pins not used by the timers are available for general-purpose input/output. table 5-15 lists the pin functions, which are the same in both the expanded and single-chip modes. table 5-15. port 6 pin functions (modes 1 to 3) usage pin functions (modes 1 to 3) i/o port p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 16-bit timer ftci ftoa ftia ftib ftic ftid ftob 8-bit timer tmci 0 ? ? tmri 0 tmo 0 tmci 1 tmri 1 tmo 1 see section 6, ?6-bit free-running timer,?and section 7, ?-bit timers?for details of the timer control bits. pins of port 6 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive a darlington pair. table 5-16 details the port 6 registers. table 5-16. port 6 registers name abbreviation read/write initial value address port 6 data direction register p6ddr w h'00 h'ffb9 port 6 data register p6dr r/w h'00 h'ffbb port 6 data direction register (p6ddr)?'ffb9 p6ddr is an 8-bit register that selects the direction of each pin in port 6. a pin functions as an output pin if the corresponding bit in p6ddr is set to ?,?and as an input pin if the bit is cleared to ?. bit 7 6 5 4 3 2 1 0 p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 101 port 6 data register (p6dr)?'ffbb p6dr is an 8-bit register containing the data for pins p6 7 to p6 0 . when the cpu reads p6dr, for output pins (p6ddr = ?? it reads the value in the p6dr latch, but for input pins (p6ddr = ??, it obtains the logic level directly from the pin, bypassing the p6dr latch. this also applies to pins used for timer input and output. pin p6 0 : this pin can be used for general-purpose input or output, and input of external clock signals to the 16-bit free-running timer and 8-bit timer 0. external clock input is selected by the cks bits of the timers. when this pin is used for timer clock input, its p6ddr bit should normally be cleared to ?;?otherwise the timer will receive the value in p6dr. pin p6 1 : this pin can be used for general-purpose input or output, or for 16-bit free-running timer output (ftoa). when timer output is selected by the oea bit of the 16-bit free-running timer, this pin is unaffected by the values in p6ddr and p6dr. pin p6 2 : this pin can be used for general-purpose input or output, and input of the ftia input capture signal to the 16-bit free-running timer. ftia input can operate simultaneously with general-purpose input or output. pin p6 3 : this pin can be used for general-purpose input or output, input of the ftib input capture signal to the 16-bit free-running timer, and input of the timer reset signal to 8-bit timer 0. ftib input operates simultaneously with the other functions. reset signal input is selected by the cclr bits of 8-bit timer 0. when this pin is used for timer reset signal input, its p6ddr bit should normally be cleared to ?;?otherwise the timer will receive the value in p6dr. pin p6 4 : this pin can be used for general-purpose input or output, input of the ftic input capture signal to the 16-bit free-running timer, or output from 8-bit timer 0. ftic input operates simultaneously with the other functions. when 8-bit timer output is selected by the os bits of 8-bit timer 0, this pin is unaffected by the values in p6ddr and p6dr. bit 7 6 5 4 3 2 1 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 102 pin p6 5 : this pin can be used for general-purpose input or output, input of the ftid input capture signal to the 16-bit free-running timer, or input of an external clock signal to 8-bit timer 1. ftid input operates simultaneously with the other functions. when external clock input is selected by the cks bits of 8-bit timer 1, the p6ddr bit of this pin should normally be cleared to ?, otherwise the timer will receive the value in p6dr. pin p6 6 : this pin can be used for general-purpose input or output, 16-bit free-running timer output (ftob), and input of the timer reset signal to 8-bit timer 1. reset signal input is selected by the cclr bits of 8-bit timer 1, and can operate simultaneously with general-purpose input or output or 16-bit timer output. when 16-bit timer output is selected by the oeb bit of the 16-bit free-running timer, this pin is unaffected by the values in p6ddr and p6dr. pin p6 7 : this pin can be used for general-purpose input or output, or output from 8-bit timer 1. when 8-bit timer output is selected by the os bits of 8-bit timer 1, this pin is unaffected by the values in p6ddr and p6dr. reset and hardware standby mode: a reset or entry to the hardware standby mode clears p6ddr and p6dr to all ?? and initializes the control registers of both the 8-bit and 16-bit timers. all pins become input port pins. software standby mode: in the software standby mode, the control registers of the 8-bit and 16- bit timers are initialized but p6ddr and p6dr remain in their previous states. all pins become input or output port pins depending on the setting of p6ddr. output pins output the values in p6dr. figures 5-12 to 5-18 show schematic diagrams of port 6. 103 figure 5-12. port 6 schematic diagram (pin p6 0 ) h8/329 u.m. '92 fig. 5-12 p6 0 rp6 reset reset wp6 wp6d r r q q d d p6 0 dr p6 0 ddr c c internal data bus wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 8-bit timer module counter clock input free-running timer module counter clock input 104 figure 5-13. port 6 schematic diagram (pin p6 1 ) h8/329 u.m. '92 fig. 5-13 rp6 reset reset wp6 wp6d r r q q d d p6 1 dr p6 1 ddr c c wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 free-running timer module output enable output-compare output p6 1 internal data bus 105 figure 5-14. port 6 schematic diagram (pin p6 2 ) h8/329 u.m. '92 fig. 5-14 p6 2 rp6 reset reset wp6 wp6d r r q q d d p6 2 dr p6 2 ddr c c internal data bus wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 input-capture input free-running timer module 106 figure 5-15. port 6 schematic diagram (pins p6 3 and p6 5 ) h8/329 u.m. '92 fig. 5-15 p6 n rp6 reset reset wp6 wp6d r r q q d d p6 n dr p6 n ddr c c internal data bus wp6d: wp6: rp6: n = 3, 5 write port 6 ddr write port 6 read port 6 8-bit timer module counter clock input counter reset input free-running timer module input-capture input 107 figure 5-16. port 6 schematic diagram (pin p6 4 ) h8/329 u.m. '92 fig. 5-16 rp6 reset reset wp6 wp6d r r q q d d p6 4 dr p6 4 ddr c c wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 8-bit timer module output enable 8-bit timer output p6 4 internal data bus free-running timer module input-capture input 108 figure 5-17. port 6 schematic diagram (pin p6 6 ) h8/329 u.m. '92 fig. 5-17 rp6 reset reset wp6 wp6d r r q q d d p6 6 dr p6 6 ddr c c wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 free-running timer module output enable output-compare output p6 6 internal data bus 8-bit timer module counter reset input 109 figure 5-18. port 6 schematic diagram (pin p6 7 ) h8/329 u.m. '92 fig. 5-18 rp6 reset reset wp6 wp6d r r q q d d p6 7 dr p6 7 ddr c c wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 8-bit timer module output enable 8-bit timer output p6 7 internal data bus 110 5.8 port 7 port 7 is an 8-bit input port that also provides the analog input pins for the a/d converter module. the pin functions are the same in both the expanded and single-chip modes. table 5-17 lists the pin functions. table 5-18 describes the port 7 data register, which simply consists of connections of the port 7 pins to the internal data bus. figure 5-19 shows a schematic diagram of port 7. table 5-17. port 7 pin functions (modes 1 to 3) usage pin functions i/o port p7 0 p7 1 p7 2 p7 3 p7 4 p7 5 p7 6 p7 7 analog input an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 table 5-18. port 7 register name abbreviation read/write initial value address port 7 data register p7dr r undetermined h'ffbe port 7 data register (p7dr)?'ffbe note: * depends on the levels of pins p7 7 to p7 0 . figure 5-19. port 7 schematic diagram bit 7 6 5 4 3 2 1 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value * * * * * * * * read/write r r r r r r r r h8/329 u.m. '92 fig. 5-19 p7n rp7: read port 7 n = 0 to 7 a/d converter module analog input internal data bus rp7 111 section 6. 16-bit free-running timer 6.1 overview the h8/329 series has an on-chip 16-bit free-running timer (frt) module that uses a 16-bit free- running counter as a time base. applications of the frt module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 6.1.1 features the features of the free-running timer module are listed below. selection of four clock sources the free-running counter can be driven by an internal clock source ( /2, /8, or /32), or an external clock input (enabling use as an external event counter). two independent comparators each comparator can generate an independent waveform. four input capture channels the current count can be captured on the rising or falling edge (selectable) of an input signal. the four input capture registers can be used separately, or in a buffer mode. counter can be cleared under program control the free-running counters can be cleared on compare-match a. seven independent interrupts compare-match a and b, input capture a to d, and overflow interrupts are requested independently. 113 6.1.2 block diagram figure 6-1 shows a block diagram of the free-running timer. figure 6-1. block diagram of 16-bit free-running timer external clock source internal clock sources clock select comparator a ocra (h/l) comparator b ocrb (h/l) bus interface internal data bus /2 /8 /32 ftci compare- clear clock ftoa ftob overflow icra (h/l) match a compare- match b capture frc (h/l) tcsr ftia ftib ftic ftid control logic module data bus tier tcr tocr ocib ocia fovi interrupt signals icia icib icic icid frc: ocra, b: icra, b, c, d: tcsr: free-running counter (16 bits) output compare register a, b (16 bits) input capture register a, b, c, d (16 bits) timer control/status register (8 bits) tier: tcr: tocr: timer interrupt enable register (8 bits) timer control register (8 bits) timer output compare control register (8 bits) icrb (h/l) icrc (h/l) icrd (h/l) 114 6.1.3 input and output pins table 6-1 lists the input and output pins of the free-running timer module. table 6-1. input and output pins of free-running timer module 6.1.4 register configuration table 6-2 lists the registers of the free-running timer module. table 6-2. register configuration notes: *1 software can write a ??to clear bits 7 to 1, but cannot write a ??in these bits. *2 ocra and ocrb share the same addresses. access is controlled by the ocrs bit in tocr. name abbreviation i/o function counter clock input ftci input input of external free-running counter clock signal output compare a ftoa output output controlled by comparator a output compare b ftob output output controlled by comparator b input capture a ftia input trigger for capturing current count into input capture register a input capture b ftib input trigger for capturing current count into input capture register b input capture c ftic input trigger for capturing current count into input capture register c input capture d ftid input trigger for capturing current count into input capture register d initial name abbreviation r/w value address timer interrupt enable register tier r/w h'01 h'ff90 timer control/status register tcsr r/(w) *1 h'00 h'ff91 free-running counter (high) frc (h) r/w h'00 h'ff92 free-running counter (low) frc (l) r/w h'00 h'ff93 output compare register a/b (high) *2 ocra/b (h) r/w h'ff h'ff94 *2 output compare register a/b (low) *2 ocra/b (l) r/w h'ff h'ff95 *2 timer control register tcr r/w h'00 h'ff96 timer output compare control register tocr r/w h'e0 h'ff97 input capture register a (high) icra (h) r h'00 h'ff98 input capture register a (low) icra (l) r h'00 h'ff99 115 table 6-2. register configuration (cont.) 6.2 register descriptions 6.2.1 free-running counter (frc)?'ff92 the frc is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. the clock source is selected by the clock select 1 and 0 bits (cks1 and cks0) of the timer control register (tcr). when the frc overflows from h'ffff to h'0000, the overflow flag (ovf) in the timer control/status register (tcsr) is set to ?. because the frc is a 16-bit register, a temporary register (temp) is used when the frc is written or read. see section 6.3, ?pu interface,?for details. the frc is initialized to h'0000 at a reset and in the standby modes. it can also be cleared by compare-match a. initial name abbreviation r/w value address input capture register b (high) icrb (h) r h'00 h'ff9a input capture register b (low) icrb (l) r h'00 h'ff9b input capture register c (high) icrc (h) r h'00 h'ff9c input capture register c (low) icrc (l) r h'00 h'ff9d input capture register d (high) icrd (h) r h'00 h'ff9e input capture register d (low) icrd (l) r h'00 h'ff9f bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value read/ r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w write 116 6.2.2 output compare registers a and b (ocra and ocrb)?'ff94 ocra and ocrb are 16-bit readable/writable registers, the contents of which are continually compared with the value in the frc. when a match is detected, the corresponding output compare flag (ocfa or ocfb) is set in the timer control/status register (tcsr). in addition, if the output enable bit (oea or oeb) in the timer output compare control register (tocr) is set to ?,?when the output compare register and frc values match, the logic level selected by the output level bit (olvla or olvlb) in the tocr is output at the output compare pin (ftoa or ftob). ocra and ocrb share the same address. they are differentiated by the ocrs bit in the tocr. a temporary register (temp) is used for write access, as explained in section 6.3, ?pu interface. ocra and ocrb are initialized to h'ffff at a reset and in the standby modes. 6.2.3 input capture registers a to d (icra to icrd)?'ff98, h'ff9a, h'ff9c, h'ff9e each input capture register is a 16-bit read-only register. when the rising or falling edge of the signal at an input capture pin (ftia to ftid) is detected, the current value of the frc is copied to the corresponding input capture register (icra to icrd).* at the same time, the corresponding input capture flag (icfa to icfd) in the timer control/status register (tcsr) is set to ?.? the input capture edge is selected by the input edge select bits (iedga to iedgd) in the timer control register (tcr). bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 value read/ r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w write bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value read/ r r r r r r r r r r r r r r r r write 117 note: * the frc contents are transferred to the input capture register regardless of the value of the input capture flag (icfa/b/c/d). input capture can be buffered by using the input capture registers in pairs. when the bufea bit in the timer control register (tcr) is set to ?,?icrc is used as a buffer register for icra as shown in figure 6-2. when an ftia input is received, the old icra contents are moved into icrc, and the new frc count is copied into icra. figure 6-2. input capture buffering similarly, when the bufeb bit in tier is set to ?,?icrd is used as a buffer register for icrb. when input capture is buffered, if the two input edge bits are set to different values (iedga iedgc or iedgb iedgd), then input capture is triggered on both the rising and falling edges of the ftia or ftib input signal. if the two input edge bits are set to the same value (iedga = iedgc or iedgb = iedgd), then input capture is triggered on only one edge. bufea: iedga: iedgc: icrc: icra: frc: buffer enable a input edge select a input edge select c input capture register c input capture register a free-running counter bufea iedga iedgc ftia edge detect and capture signal generating circuit frc icrc icra fig. 6-2 118 table 6-3. buffered input capture edge selection (example) iedga iedgc input capture edge 0 0 captured on falling edge of input capture a (ftia) (initial value) 0 1 captured on both rising and falling edges of input capture a (ftia) 1 0 1 1 captured on rising edge of input capture a (ftia) because the input capture registers are 16-bit registers, a temporary register (temp) is used when they are read. see section 6.3, ?pu interface,?for details. to ensure input capture, the width of the input capture pulse (ftia, ftib, ftic, ftid) should be at least 1.5 system clock periods (1.5). when triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. figure 6-3. minimum input capture pulse width ftia, ftib, ftic, or ftid 119 the input capture registers are initialized to h'0000 at a reset and in the standby modes. note: when input capture is detected, the frc value is transferred to the input capture register even if the input capture flag is already set. 6.2.4 timer interrupt enable register (tier)?'ff90 the tier is an 8-bit readable/writable register that enables and disables interrupts. the tier is initialized to h'01 (all interrupts disabled) at a reset and in the standby modes. bit 7?nput capture interrupt a enable (iciae): this bit selects whether to request input capture interrupt a (icia) when input capture flag a (icfa) in the timer status/control register (tcsr) is set to ?. bit 6?nput capture interrupt b enable (icibe): this bit selects whether to request input capture interrupt b (icib) when input capture flag b (icfb) in the timer status/control register (tcsr) is set to ?. bit 5?nput capture interrupt c enable (icice): this bit selects whether to request input capture interrupt c (icic) when input capture flag c (icfc) in the timer status/control register (tcsr) is set to ?. bit 7 6 5 4 3 2 1 0 iciae icibe icice icide ociae ocibe ovie initial value 0 0 0 0 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w bit 7 iciae description 0 input capture interrupt request a (icia) is disabled. (initial value) 1 input capture interrupt request a (icia) is enabled. bit 6 icibe description 0 input capture interrupt request b (icib) is disabled. (initial value) 1 input capture interrupt request b (icib) is enabled. 120 bit 4?nput capture interrupt d enable (icide): this bit selects whether to request input capture interrupt d (icid) when input capture flag d (icfd) in the timer status/control register (tcsr) is set to ?. bit 3?utput compare interrupt a enable (ociae): this bit selects whether to request output compare interrupt a (ocia) when output compare flag a (ocfa) in the timer status/control register (tcsr) is set to ?. bit 2?utput compare interrupt b enable (ocibe): this bit selects whether to request output compare interrupt b (ocib) when output compare flag b (ocfb) in the timer status/control register (tcsr) is set to ?. bit 1?imer overflow interrupt enable (ovie): this bit selects whether to request a free- running timer overflow interrupt (fovi) when the timer overflow flag (ovf) in the timer status/control register (tcsr) is set to ?. bit 5 icice description 0 input capture interrupt request c (icic) is disabled. (initial value) 1 input capture interrupt request c (icic) is enabled. bit 4 icide description 0 input capture interrupt request d (icid) is disabled. (initial value) 1 input capture interrupt request d (icid) is enabled. bit 3 ociae description 0 output compare interrupt request a (ocia) is disabled. (initial value) 1 output compare interrupt request a (ocia) is enabled. bit 2 ocibe description 0 output compare interrupt request b (ocib) is disabled. (initial value) 1 output compare interrupt request b (ocib) is enabled. 121 bit 0?eserved: this bit cannot be modified and is always read as ?. 6.2.5 timer control/status register (tcsr)?'ff91 the tcsr is an 8-bit readable and partially writable* register that contains the seven interrupt flags and specifies whether to clear the counter on compare-match a (when the frc and ocra values match). note: * software can write a ??in bits 7 to 1 to clear the flags, but cannot write a ??in these bits. the tcsr is initialized to h'00 at a reset and in the standby modes. bit 7?nput capture flag a (icfa): this status bit is set to ??to flag an input capture a event. if bufea = ?,?icfa indicates that the frc value has been copied to icra. if bufea = ?,?icfa indicates that the old icra value has been moved into icrc and the new frc value has been copied to icra. icfa must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 1 ovie description 0 timer overflow interrupt request (fovi) is disabled. (initial value) 1 timer overflow interrupt request (fovi) is enabled. bit 7 6 5 4 3 2 1 0 icfa icfb icfc icfd ocfa ocfb ovf cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/w bit 7 icfa description 0 to clear icfa, the cpu must read icfa after it (initial value) has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when an ftia input signal causes the frc value to be copied to icra. 122 bit 6?nput capture flag b (icfb): this status bit is set to ??to flag an input capture b event. if bufeb = ?,?icfb indicates that the frc value has been copied to icrb. if bufeb = ?,?icfb indicates that the old icrb value has been moved into icrc and the new frc value has been copied to icrb. icfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 5?nput capture flag c (icfc): this status bit is set to ??to flag input of a rising or falling edge of ftic as selected by the iedgc bit. when bufea = ?,?this indicates capture of the frc count in icrc. when bufea = ?,?however, the frc count is not captured, so icfc becomes simply an external interrupt flag. in other words, the buffer mode frees ftic for use as a general-purpose interrupt signal (which can be enabled or disabled by the icice bit). icfc must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4?nput capture flag d (icfd): this status bit is set to ??to flag input of a rising or falling edge of ftid as selected by the iedgd bit. when bufeb = ?,?this indicates capture of the frc count in icrd. when bufeb = ?,?however, the frc count is not captured, so icfd becomes simply an external interrupt flag. in other words, the buffer mode frees ftid for use as a general-purpose interrupt signal (which can be enabled or disabled by the icide bit). icfd must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6 icfb description 0 to clear icfb, the cpu must read icfb after it (initial value) has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when an ftib input signal causes the frc value to be copied to icrb. bit 5 icfc description 0 to clear icfc, the cpu must read icfc after it (initial value) has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when an ftic input signal is received. 123 bit 3?utput compare flag a (ocfa): this status flag is set to ??when the frc value matches the ocra value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 2?utput compare flag b (ocfb): this status flag is set to ??when the frc value matches the ocrb value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 1?imer overflow flag (ovf): this status flag is set to ??when the frc overflows (changes from h'ffff to h'0000). this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4 icfd description 0 to clear icfd, the cpu must read icfd after it (initial value) has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when an ftid input signal is received. bit 3 ocfa description 0 to clear ocfa, the cpu must read ocfa after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when frc = ocra. bit 2 ocfb description 0 to clear ocfb, the cpu must read ocfb after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when frc = ocrb. bit 1 ovf description 0 to clear ovf, the cpu must read ovf after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when frc changes from h'ffff to h'0000. 124 bit 0?ounter clear a (cclra): this bit selects whether to clear the frc at compare-match a (when the frc and ocra values match). 6.2.6 timer control register (tcr)?'ff96 the tcr is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the frc clock source. the tcr is initialized to h'00 at a reset and in the standby modes. bit 7?nput edge select a (iedga): this bit causes input capture a events to be recognized on the selected edge of the input capture a signal (ftia). bit 6?nput edge select b (iedgb): this bit causes input capture b events to be recognized on the selected edge of the input capture b signal (ftib). bit 0 cclra description 0 the frc is not cleared. (initial value) 1 the frc is cleared at compare-match a. bit 7 6 5 4 3 2 1 0 iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7 iedga description 0 input capture a events are recognized on the falling edge of ftia. (initial value) 1 input capture a events are recognized on the rising edge of ftia. bit 6 iedgb description 0 input capture b events are recognized on the falling edge of ftib. (initial value) 1 input capture b events are recognized on the rising edge of ftib. 125 bit 5?nput edge select c (iedgc): this bit causes input capture c events to be recognized on the selected edge of the input capture c signal (ftic). bit 4?nput edge select d (iedgd): this bit causes input capture d events to be recognized on the selected edge of the input capture d signal (ftid). bit 3?uffer enable a (bufea): this bit selects whether to use icrc as a buffer register for icra. bit 2?uffer enable b (bufeb): this bit selects whether to use icrd as a buffer register for icrb. bits 1 and 0?lock select (cks1 and cks0): these bits select external clock input or one of three internal clock sources for the frc. external clock pulses are counted on the rising edge. bit 5 iedgc description 0 input capture c events are recognized on the falling edge of ftic. (initial value) 1 input capture c events are recognized on the rising edge of ftic. bit 4 iedgd description 0 input capture d events are recognized on the falling edge of ftid. (initial value) 1 input capture d events are recognized on the rising edge of ftid. bit 3 bufea description 0 icrc is used for input capture c. (initial value) 1 icrc is used as a buffer register for input capture a. input c is not captured. bit 2 bufeb description 0 icrd is used for input capture d. (initial value) 1 icrd is used as a buffer register for input capture b. input d is not captured. 126 6.2.7 timer output compare control register (tocr)?'ff97 the tocr is an 8-bit readable/writable register that controls the output compare function. the tocr is initialized to h'e0 at a reset and in the standby modes. bits 7 to 5?eserved: these bits cannot be modified and are always read as ?. bit 4?utput compare register select (ocrs): when the cpu accesses addresses h'ff94 and h'ff95, this bit directs the access to either ocra or ocrb. these two registers share the same addresses as follows: upper byte of ocra and upper byte of ocrb: h'ff94 lower byte of ocra and lower byte of ocrb: h'ff95 bit 3?utput enable a (oea): this bit enables or disables output of the output compare a signal (ftoa). bit 1 bit 0 cks1 cks0 description 0 0 /2 internal clock source (initial value) 0 1 /8 internal clock source 1 0 /32 internal clock source 1 1 external clock source (rising edge) bit 7 6 5 4 3 2 1 0 ocrs oea oeb olvla olvlb initial value 1 1 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w bit 4 ocrs description 0 the cpu can access ocra. (initial value) 1 the cpu can access ocrb. bit 3 oea description 0 output compare a output is disabled. (initial value) 1 output compare a output is enabled. 127 bit 2?utput enable b (oeb): this bit enables or disables output of the output compare b signal (ftob). bit 1?utput level a (olvla): this bit selects the logic level to be output at the ftoa pin when the frc and ocra values match. bit 0?utput level b (olvlb): this bit selects the logic level to be output at the ftob pin when the frc and ocrb values match. 6.3 cpu interface the free-running counter (frc), output compare registers (ocra and ocrb), and input capture registers (icra to icrd) are 16-bit registers, but they are connected to an 8-bit data bus. when the cpu accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (temp). these registers are written and read as follows: register write when the cpu writes to the upper byte, the byte of write data is placed in temp. next, when the cpu writes to the lower byte, this byte of data is combined with the byte in temp and all 16 bits are written in the register simultaneously. bit 2 oeb description 0 output compare b output is disabled. (initial value) 1 output compare b output is enabled. bit 1 olvla description 0 a ??logic level (low) is output for compare-match a. (initial value) 1 a ??logic level (high) is output for compare-match a. bit 0 olvlb description 0 a ??logic level (low) is output for compare-match b. (initial value) 1 a ??logic level (high) is output for compare-match b. 128 register read when the cpu reads the upper byte, the upper byte of data is sent to the cpu and the lower byte is placed in temp. when the cpu reads the lower byte, it receives the value in temp. (as an exception, when the cpu reads ocra or ocrb, it reads both the upper and lower bytes directly, without using temp.) programs that access these registers should normally use word access. equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. coding examples to write the contents of general register r0 to ocra: mov.w r0, @ocra to transfer the contents of icra to general register r0: mov.w @icra, r0 figure 6-4 shows the data flow when the frc is accessed. the other registers are accessed in the same way. figure 6-4 (a). write access to frc (when cpu writes h'aa55) module data bus (1) upper byte write bus interface cpu writes data h'aa frc h [ ] frc l [ ] temp [h'aa] (2) lower byte write bus interface module data bus cpu writes data h'55 temp [h'aa] frc h [h'aa] frc l [h'55] h8/329 u.m. '92 fig. 6-4 (a) 129 figure 6-4 (b). read access to frc (when frc contains h'aa55) 6.4 operation 6.4.1 frc incrementation timing the frc increments on a pulse generated once for each period of the selected (internal or external) clock source. the clock source is selected by bits cks0 and cks1 in the tcr. internal clock: the internal clock sources ( /2, /8, /32) are created from the system clock ( ) by a prescaler. the frc increments on a pulse generated from the falling edge of the prescaler output. see figure 6-5. (1) upper byte read bus interface module data bus cpu reads data h'aa temp [h'55] frc h [h'aa] frc l [h'55] (2) lower byte read bus interface module data bus cpu reads data h'55 temp [h'55] frc h [ ] frc l [ ] h8/329 u.m. '92 fig. 6-4 (b) 130 figure 6-5. increment timing for internal clock source external clock: if external clock input is selected, the frc increments on the rising edge of the ftci clock signal. figure 6-6 shows the increment timing. the pulse width of the external clock signal must be at least 1.5 system clock ( ) periods. the counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. figure 6-6. increment timing for external clock source figure 6-7. minimum external clock pulse width internal clock frc clock pulse frc n ?1 n n + 1 fig. 6-5 n n + 1 ftci frc frc clock pulse ftci 131 6.4.2 output compare timing (1) setting of output compare flags a and b (ocfa and ocfb): the output compare flags are set to ??by an internal compare-match signal generated when the frc value matches the ocra or ocrb value. this compare-match signal is generated at the last state in which the two values match, just before the frc increments to a new value. accordingly, when the frc and ocr values match, the compare-match signal is not generated until the next period of the clock source. figure 6-8 shows the timing of the setting of the output compare flags. figure 6-8. setting of output compare flags n n n + 1 frc ocr internal compare- match signal ocfa or ocfb ocra or ocrb 132 (2) output timing: when a compare-match occurs, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). figure 6-9 shows the timing of this operation for compare-match a. figure 6-9. timing of output compare a (3) frc clear timing: if the cclra bit in the tcsr is set to ?,?the frc is cleared when compare-match a occurs. figure 6-10 shows the timing of this operation. figure 6-10. clearing of frc by compare-match a 6.4.3 input capture timing (1) input capture timing: an internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin ftix (x = a, b, c, d), as selected by the corresponding iedgx bit in tcr. figure 6-11 shows the usual input capture timing when the rising edge is selected (iedgx = ??. internal compare- match a signal olvla ftoa note: * cleared by software frc ocra n n n n + 1 clear * n n + 1 figure 6-9 internal compare- match a signal frc n h'0000 fig. 6-10 133 figure 6-11. input capture timing (usual case) if the upper byte of icrx is being read when the input capture signal arrives, the internal input capture signal is delayed by one state. figure 6-12 shows the timing for this case. figure 6-12. input capture timing (1-state delay) in buffer mode, this delay occurs if the cpu is reading either of the two registers concerned. when icra and icrc are used in buffer mode, for example, if the upper byte of either icra or icrc is being read when the ftia input arrives, the internal input capture signal is delayed by one state. figure 6-13 shows the timing for this case. the case of icrb and icrd is similar. figure 6-13. input capture timing (1-state delay, buffer mode) input at fti pin internal input capture signal read cycle: cpu reads upper byte of icr t 1 t 2 t 3 input at fti pin internal input capture signal figure 6-13 t t t read cycle: cpu reads upper byte of icra or icrc input at ftia pin internal input capture signal 1 2 3 figure 6-14 134 figure 6-14 shows how input capture operates when icra and icrc are used in buffer mode and iedga and iedgc are set to different values (iedga = 0 and iedgc = 1, or iedga = 1 and iedgc = 0), so that input capture is performed on both the rising and falling edges of ftia. figure 6-14. buffered input capture with both edges selected in this mode, ftic does not cause the frc contents to be copied to icrc. however, input capture flag c still sets on the edge of ftic selected by iedgc, and if the interrupt enable bit (icice) is set, a cpu interrupt is requested. the situation when icrb and icrd are used in buffer mode is similar. n n + 1 n n + 1 n m m m n n n m ftia internal input capture signal frc icra icrc figure 6-14 135 (2) timing of input capture flag (icf) setting: the input capture flag icfx (x = a, b, c, d) is set to ??by the internal input capture signal. figure 6-15 shows the timing of this operation. figure 6-15. setting of input capture flag 6.4.4 setting of frc overflow flag (ovf) the frc overflow flag (ovf) is set to ??when the frc overflows (changes from h'ffff to h'0000). figure 6-16 shows the timing of this operation. figure 6-16. setting of overflow flag (ovf) ovf frc internal overflow signal h'ffff h'0000 internal input capture signal icfa/b/c/d frc icra/b/c/d n n figure 6-15 136 6.5 interrupts the free-running timer can request seven types of interrupts: input capture a to d (icia, icib, icic, icid), output compare a and b (ocia and ocib), and overflow (fovi). each interrupt is requested when the corresponding enable and flag bits are set. independent signals are sent to the interrupt controller for each type of interrupt. table 6-4 lists information about these interrupts. table 6-4. free-running timer interrupts 6.6 sample application in the example below, the free-running timer is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. the programming is as follows: (1) the cclra bit in the tcsr is set to ?. (2) each time a compare-match interrupt occurs, software inverts the corresponding output level bit in tocr (olvla or olvlb). figure 6-17. square-wave output (example) interrupt description priority icia requested when icfa and iciae are set high icib requested when icfb and icibe are set icic requested when icfc and icice are set icid requested when icfd and icide are set ocia requested when ocfa and ociae are set ocib requested when ocfb and ocibe are set fovi requested when ovf and ovie are set low frc h'ffff ocra ocrb h'0000 ftoa ftob clear counter fig. 6-17 137 6.7 application notes application programmers should note that the following types of contention can occur in the free- running timers. (1) contention between frc write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. figure 6-18 shows this type of contention. figure 6-18. frc write-clear contention write cycle: cpu write to lower byte of frc frc address n h'0000 t 1 t 2 t 3 internal address bus internal write signal frc clear signal frc figure 6-21 138 (2) contention between frc write and increment: if an frc increment pulse is generated during the t 3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and the frc is not incremented. figure 6-19 shows this type of contention. figure 6-19. frc write-increment contention write cycle: cpu write to lower byte of frc frc address internal address bus internal write signal frc clock pulse frc n m t t t write data 1 2 3 figure 6-22 139 (3) contention between ocr write and compare-match: if a compare-match occurs during the t 3 state of a write cycle to the lower byte of ocra or ocrb, the write takes priority and the compare-match signal is inhibited. figure 6-20 shows this type of contention. figure 6-20. contention between ocr write and compare-match write cycle: cpu write to lower byte of ocra or ocrb ocr address n n + 1 n m inhibited write data internal address bus internal write signal compare-match a or b signal ocra or ocrb frc t 1 t t 2 3 140 (4) incrementation caused by changing of internal clock source: when an internal clock source is changed, the changeover may cause the frc to increment. this depends on the time at which the clock select bits (cks1 and cks0) are rewritten, as shown in table 6-5. the pulse that increments the frc is generated at the falling edge of the internal clock source. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 6-5, the changeover generates a falling edge that triggers the frc increment clock pulse. switching between an internal and external clock source can also cause the frc to increment. table 6-5. effect of changing internal clock sources no. description timing chart low low: cks1 and cks0 are 1 rewritten while both clock sources are low. low high: cks1 and cks0 are 2 rewritten while old clock source is low and new clock source is high. old clock source new clock source frc clock pulse frc cks rewrite n n + 1 old clock source new clock source frc clock pulse frc cks rewrite n n + 1 n + 2 141 table 6-5. effect of changing internal clock sources (cont.) note: * the switching of clock sources is regarded as a falling edge that increments the frc. no. description timing chart high low: cks1 and cks0 are 3 rewritten while old clock source is high and new clock source is low. high high: cks1 and cks0 are 4 rewritten while both clock sources are high. old clock source new clock source frc clock pulse frc n n + 1 cks rewrite n + 2 old clock source new clock source frc clock pulse frc n n + 1 n + 2 cks rewrite * figure 6-4-3 142 section 7. 8-bit timers 7.1 overview the h8/329 series includes an 8-bit timer module with two channels (tmr0 and tmr1). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare-match events. one application of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle. 7.1.1 features the features of the 8-bit timer module are listed below. selection of seven clock sources the counters can be driven by one of six internal clock signals or an external clock input (enabling use as an external event counter). selection of three ways to clear the counters the counters can be cleared on compare-match a or b, or by an external reset signal. timer output controlled by two time constants the timer output signal in each channel is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty factor. three independent interrupts compare-match a and b and overflow interrupts can be requested independently. 7.1.2 block diagram figure 7-1 shows a block diagram of one channel in the 8-bit timer module. the other channel is identical. 143 figure 7-1. block diagram of 8-bit timer 7.1.3 input and output pins table 7-1 lists the input and output pins of the 8-bit timer. table 7-1. input and output pins of 8-bit timer h161 h8/337 h.m '91 fig. 7-1 external clock source tmci tmo tmri internal clock sources channel 0 channel 1 /2 /8 /32 /64 /256 /1024 /2 /8 /64 /128 /1024 /2048 clock overflow clear compare-match b control logic clock select tcora comparator a tcnt comparator b tcorb tcsr tcr module data bus bus interface internal data bus cmia cmib ovi interrupt signals tcr: tcsr: tcora: tcorb: tcnt: timer control register (8 bits) timer control status register (8 bits) time constant register a (8 bits) time constant register b (8 bits) timer counter compare-match a abbreviation name tmr0 tmr1 i/o function timer output tmo 0 tmo 1 output output controlled by compare-match timer clock input tmci 0 tmci 1 input external clock source for the counter timer reset input tmri 0 tmri 1 input external reset signal for the counter 144 7.1.4 register configuration table 7-2 lists the registers of the 8-bit timer module. each channel has an independent set of registers. table 7-2. 8-bit timer registers note: * software can write a ??to clear bits 7 to 5, but cannot write a ??in these bits. 7.2 register descriptions 7.2.1 timer counter (tcnt)?'ffcc (tmr0), h'ffd4 (tmr1) bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w each timer counter (tcnt) is an 8-bit up-counter that increments on a pulse generated from an internal or external clock source selected by clock select bits 2 to 0 (cks2 to cks0) of the timer control register (tcr). the cpu can always read or write the timer counter. the timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. clock clear bits 1 and 0 (cclr1 and cclr0) of the timer control register select the method of clearing. when a timer counter overflows from h'ff to h'00, the overflow flag (ovf) in the timer control/status register (tcsr) is set to ?. address name abbreviation r/w initial value tmr0 tmr1 timer control register tcr r/w h'00 h'ffc8 h'ffd0 timer control/status register tcsr r/(w)* h'10 h'ffc9 h'ffd1 timer constant register a tcora r/w h'ff h'ffca h'ffd2 timer constant register b tcorb r/w h'ff h'ffcb h'ffd3 timer counter tcnt r/w h'00 h'ffcc h'ffd4 serial/timer control register stcr r/w h'f8 h'ffc3 h'ffc3 145 the timer counters are initialized to h'00 at a reset and in the standby modes. bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 146 7.2.2 time constant registers a and b (tcora and tcorb)?'ffca and h'ffcb (tmr0), h'ffd2 and h'ffd3 (tmr1) tcora and tcorb are 8-bit readable/writable registers. the timer count is continually compared with the constants written in these registers. when a match is detected, the corresponding compare-match flag (cmfa or cmfb) is set in the timer control/status register (tcsr). the timer output signal (tmo0 or tmo1) is controlled by these compare-match signals as specified by output select bits 3 to 0 (os3 to os0) in the timer control/status register (tcsr). tcora and tcorb are initialized to h'ff at a reset and in the standby modes. compare-match is not detected during the t 3 state of a write cycle to tcora or tcorb. see item (3) in section 7.6, ?pplication notes. 7.2.3 timer control register (tcr)?'ffc8 (tmr0), h'ffd0 (tmr1) each tcr is an 8-bit readable/writable register that selects the clock source and the time at which bit 7 cmieb description 0 compare-match interrupt request b (cmib) is disabled. (initial value) 1 compare-match interrupt request b (cmib) is enabled. bit 6 cmiea description 0 compare-match interrupt request a (cmia) is disabled. (initial value) 1 compare-match interrupt request a (cmia) is enabled. bit 5 ovie description 0 the timer overflow interrupt request (ovi) is disabled. (initial value) 1 the timer overflow interrupt request (ovi) is enabled. bit 4 bit 3 cclr1 cclr0 description 0 0 not cleared. (initial value) 0 1 cleared on compare-match a. 1 0 cleared on compare-match b. 1 1 cleared on rising edge of external reset input signal. 147 bits 2, 1, and 0?lock select (cks2, cks1, and cks0): these bits and bits icks1 and icks0 in the serial/timer control register (stcr) select the internal or external clock source for the timer counter. six internal clock sources, derived by prescaling the system clock, are available for each timer channel. for internal clock sources the counter is incremented on the falling edge of the internal clock. for an external clock source, these bits can select whether to increment the counter on the rising or falling edge of the clock input, or on both edges. tcr stcr bit 2 bit 1 bit 0 bit 1 bit 0 channel cks2 cks1 cks0 icks1 icks0 description 0 0 0 0 no clock source (timer stopped) (initial value) 0 0 1 0 /8 internal clock, counted on falling edge 0 0 1 1 /2 internal clock, counted on falling edge 0 1 0 0 /64 internal clock, counted on falling edge 0 1 0 1 /32 internal clock, counted on falling edge 0 1 1 0 /1024 internal clock, counted on falling edge 0 1 1 1 /256 internal clock, counted on falling edge 1 0 0 no clock source (timer stopped) 1 0 1 external clock source, counted on rising edge 1 1 0 external clock source, counted on falling edge 1 1 1 external clock source, counted on both rising and falling edges 1 0 0 0 no clock source (timer stopped) (initial value) 0 0 1 0 /8 internal clock, counted on falling edge 0 0 1 1 /2 internal clock, counted on falling edge 0 1 0 0 /64 internal clock, counted on falling edge 0 1 0 1 /128 internal clock, counted on falling edge 0 1 1 0 /1024 internal clock, counted on falling edge 0 1 1 1 /2048 internal clock, counted on falling edge 1 0 0 no clock source (timer stopped) 1 0 1 external clock source, counted on rising edge 1 1 0 external clock source, counted on falling edge 1 1 1 external clock source, counted on both rising and falling edges 148 the timer counter is cleared, and enables interrupts. the tcrs are initialized to h'00 at a reset and in the standby modes. for timing diagrams, see section 7.3, ?peration. bit 7?ompare-match interrupt enable b (cmieb): this bit selects whether to request compare-match interrupt b (cmib) when compare-match flag b (cmfb) in the timer control/status register (tcsr) is set to ?. bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf os3 os2 os1 os0 initial value 0 0 0 1 0 0 0 0 read/write r/(w)* r/(w)* r/(w)* r/w r/w r/w r/w bit 7 cmfb description 0 to clear cmfb, the cpu must read cmfb after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when tcnt = tcorb. bit 6 cmfa description 0 to clear cmfa, the cpu must read cmfa after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when tcnt = tcora. 149 bit 6?ompare-match interrupt enable a (cmiea): this bit selects whether to request compare-match interrupt a (cmia) when compare-match flag a (cmfa) in the timer control/status register (tcsr) is set to ?. bit 5?imer overflow interrupt enable (ovie): this bit selects whether to request a timer overflow interrupt (ovi) when the overflow flag (ovf) in the timer control/status register (tcsr) is set to ?. bits 4 and 3?ounter clear 1 and 0 (cclr1 and cclr0): these bits select how the timer counter is cleared: by compare-match a or b or by an external reset input. bit 5 ovf description 0 to clear ovf, the cpu must read ovf after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when tcnt changes from h'ff to h'00. bit 3 bit 2 os3 os2 description 0 0 no change when compare-match b occurs. (initial value) 0 1 output changes to ??when compare-match b occurs. 1 0 output changes to ??when compare-match b occurs. 1 1 output inverts (toggles) when compare-match b occurs. bit 1 bit 0 os1 os0 description 0 0 no change when compare-match a occurs. (initial value) 0 1 output changes to ??when compare-match a occurs. 1 0 output changes to ??when compare-match a occurs. 1 1 output inverts (toggles) when compare-match a occurs. 150 7.2.5 serial/timer control register (stcr)?'ffc3 bit 7 6 5 4 3 2 1 0 mpe icks1 icks0 initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w the stcr is an 8-bit readable/writable register that controls the serial communication interface and selects internal clock sources for the timer counters. the stcr is initialized to h'f8 at a reset. bits 7 to 3?eserved: these bits cannot be modified and are always read as ?. bit 2?ultiprocessor enable (mpe): controls the operating mode of the serial communication interface. for details, see section 8, ?erial communication interface. bits 1 and 0?nternal clock source select 1 and 0 (icks1 and icks0): these bits and bits cks2 to cks0 in the tcr select clock sources for the timer counters. for details, see section 7.2.3, ?imer control register. 151 7.2.4 timer control/status register (tcsr)?'ffc9 (tmr0), h'ffd1 (tmr1) note: * software can write a ??in bits 7 to 5 to clear the flags, but cannot write a ??in these bits. the tcsr is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal. the tcsr is initialized to h'10 at a reset and in the standby modes. bit 7?ompare-match flag b (cmfb): this status flag is set to ??when the timer count matches the time constant set in tcorb. cmfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6?ompare-match flag a (cmfa): this status flag is set to ??when the timer count matches the time constant set in tcora. cmfa must be cleared by software. it is set by hardware, however, and cannot be set by software. figure 7-2 n? n+1 n internal clock tcnt clock pulse tcnt 152 bit 5?imer overflow flag (ovf): this status flag is set to ??when the timer count overflows (changes from h'ff to h'00). ovf must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4?eserved: this bit cannot be modified and is always read as ?. bits 3 to 0?utput select 3 to 0 (os3 to os0): these bits specify the effect of compare-match events on the timer output signal (tcor or tcnt). bits os3 and os2 control the effect of compare-match b on the output level. bits os1 and os0 control the effect of compare-match a on the output level. external clock source tcnt clock pulse tcnt n n + 1 n ?1 fig. 7-3 tmci tmci minimum tmci pulse width (single-edge incrementation) minimum tmci pulse width (double-edge incrementation) 153 if compare-match a and b occur simultaneously, any conflict is resolved as explained in item (4) in section 7.6, ?pplication notes. after a reset, the timer output is ??until the first compare-match event. when all four output select bits are cleared to ??the timer output signal is disabled. tcnt tcor internal compare-match signal cmf n n + 1 n figure 7-5 internal compare-match a signal timer output (tmo) 154 7.3 operation 7.3.1 tcnt incrementation timing the timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. internal clock: internal clock sources are created from the system clock by a prescaler. the counter increments on an internal tcnt clock pulse generated from the falling edge of the prescaler output, as shown in figure 7-2. bits cks2 to cks0 of the tcr and bits icks1 and icks0 of the stcr can select one of the six internal clocks. figure 7-2. count timing for internal clock input external clock: if external clock input (tmci) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. figure 7-3 shows incrementation on both edges of the external clock signal. the external clock pulse width must be at least 1.5 system clock periods for incrementation on a n h'00 internal compare-match signal tcnt external reset input (tmri) internal clear pulse tcnt n n ?1 h'00 155 single edge, and at least 2.5 system clock periods for incrementation on both edges. see figure 7-4. the counter will not increment correctly if the pulse width is shorter than these values. h'00 tcnt internal overflow signal ovf h'ff 156 figure 7-3. count timing for external clock input figure 7-4. minimum external clock pulse widths (example) 7.3.2 compare match timing (1) setting of compare-match flags a and b (cmfa and cmfb): the compare-match flags are set to ??by an internal compare-match signal generated when the timer count matches the time constant in tcnt or tcor. the compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. interrupt description priority cmia requested when cmfa and cmiea are set high cmib requested when cmfb and cmieb are set ovi requested when ovf and ovie are set low h'ff tcora tcorb h'00 tmo pin clear counter tcnt figure 7-10 157 accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. figure 7-5 shows the timing of the setting of the compare-match flags. figure 7-5. setting of compare-match flags (2) output timing: when a compare-match event occurs, the timer output (tmo0 or tmo1) changes as specified by the output select bits (os3 to os0) in the tcsr. depending on these bits, the output can remain the same, change to ?,?change to ?,?or toggle. figure 7-6 shows the timing when the output is set to toggle on compare-match a. figure 7-6. timing of timer output internal address bus internal write signal counter clear signal tcnt n h'00 tcnt address write cycle: cpu writes to tcnt t 1 t 2 t 3 figure 7-11 158 (3) timing of compare-match clear: depending on the cclr1 and cclr0 bits in the tcr, the timer counter can be cleared when compare-match a or b occurs. figure 7-7 shows the timing of this operation. figure 7-7. timing of compare-match clear 7.3.3 external reset of tcnt when the cclr1 and cclr0 bits in the tcr are both set to ?,?the timer counter is cleared on the rising edge of an external reset input. figure 7-8 shows the timing of this operation. the timer reset pulse width must be at least 1.5 system clock periods. figure 7-8. timing of external reset internal address bus internal write signal tcnt clock pulse tcnt n m tcnt address write cycle: cpu writes to tcnt t 1 write data t 2 t 3 figure 7-12 159 7.3.4 setting of tcsr overflow flag (ovf) the overflow flag (ovf) is set to ??when the timer count overflows (changes from h'ff to h'00). figure 7-9 shows the timing of this operation. figure 7-9. setting of overflow flag (ovf) internal address bus internal write signal tcnt n m tcor address write cycle: cpu writes to tcora or tcorb n n + 1 tcora or tcorb compare-match a or b signal t 1 inhibited tcor write data figure 7-13 t 2 t 3 output selection priority toggle high ??output ??output no change low 160 7.4 interrupts each channel in the 8-bit timer can generate three types of interrupts: compare-match a and b (cmia and cmib), and overflow (ovi). each interrupt is requested when the corresponding enable bits are set in the tcr and tcsr. independent signals are sent to the interrupt controller for each interrupt. table 7-3 lists information about these interrupts. table 7-3. 8-bit timer interrupts 7.5 sample application in the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle. the control bits are set as follows: (1) in the tcr, cclr1 is cleared to ??and cclr0 is set to ??so that the timer counter is cleared when its value matches the constant in tcora. no. description timing chart low ? low *1 : clock select bits are 1 rewritten while both clock sources are low. low ? high *2 : clock select bits are 2 rewritten while old clock source is low and new clock source is high. n + 1 n old clock source new clock source tcnt clock pulse tcnt cks rewrite n + 1 n old clock source new clock source tcnt clock pulse tcnt cks rewrite n + 2 161 (2) in the tcsr, bits os3 to os0 are set to ?110,?causing the output to change to ??on compare-match a and to ??on compare-match b. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. figure 7-10. example of pulse output 7.6 application notes application programmers should note that the following types of contention can occur in the 8-bit timer. (1) contention between tcnt write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. figure 7-11 shows this type of contention. no. description timing chart high ? low *1 : clock select bits are 3 rewritten while old clock source is high and new clock source is low. high ? high: clock select bits are 4 rewritten while both clock sources are high. old clock source new clock source tcnt clock pulse tcnt cks rewrite n n + 1 n + 2 * 3 *2 n + 1 n old clock source new clock source tcnt clock pulse tcnt cks rewrite n + 2 162 section 8. serial communication interface 8.1 overview the h8/329 series includes a serial communication interface (sci) for transferring serial data to and from other chips. either synchronous or asynchronous communication can be selected. 8.1.1 features the features of the on-chip serial communication interface are: asynchronous mode the h8/329 series can communicate with a uart (universal asynchronous receiver/transmitter), acia (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. it also has a multiprocessor communication function for communication with other processors. twelve data formats are available. data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even, odd, or none multiprocessor bit: ??or ? error detection: parity, overrun, and framing errors break detection: when a framing error occurs, the break condition can be detected by reading the level of the rxd line directly. synchronous mode the sci can communicate with chips able to perform clocked synchronous data transfer. data length: 8 bits error detection: overrun errors full duplex communication the transmitting and receiving sections are independent, so each channel can transmit and receive simultaneously. both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. built-in baud rate generator any specified baud rate can be generated. internal or external clock source the sci can operate on an internal clock signal from baud rate generator, or an external clock signal input at the sck pin. four interrupts tdr-empty, tsr-empty, receive-end, and receive-error interrupts are requested independently. 163 8.1.2 block diagram figure 8-1 shows a block diagram of the serial communication interface. figure 8-1. block diagram of serial communication interface tdr bus interface internal data bus module data bus parity generate clock parity check tsr /4 /16 /64 rxd txd txi rxi eri interrupt signals external clock source internal clock rdr rsr sck brr communi- cation control ssr scr smr baud rate generator rsr: rdr: tsr: tdr: smr: scr: ssr: brr: receive shift register (8 bits) receive data register (8 bits) transmit shift register (8 bits) transmit data register (8 bits) serial mode register (8 bits) serial control register (8 bits) serial status register (8 bits) bit rate register (8 bits) figure 8-1 tei 164 8.1.3 input and output pins table 8-1 lists the input and output pins used by the sci module. table 8-1. sci input/output pins name abbr. i/o function serial clock sck input/output serial clock input and output. receive data rxd input receive data input. transmit data txd output transmit data output. 8.1.4 register configuration table 8-2 lists the sci registers. these registers specify the operating mode (synchronous or asynchronous), data format and bit rate, and control the transmit and receive sections. table 8-2. sci registers name abbr. r/w value address receive shift register rsr receive data register rdr r h'00 h'ffdd transmit shift register tsr transmit data register tdr r/w h'ff h'ffdb serial mode register smr r/w h'00 h'ffd8 serial control register scr r/w h'00 h'ffda serial status register ssr r/(w)* h'84 h'ffdc bit rate register brr r/w h'ff h'ffd9 serial/timer control register stcr r/w h'f8 h'ffc3 note: * software can write a ??to clear the flags in bits 7 to 3, but cannot write ??in these bits. 165 8.2 register descriptions 8.2.1 receive shift register (rsr) bit 7 6 5 4 3 2 1 0 read/write the rsr receives incoming data bits. when one data character has been received, it is transferred to the receive data register (rdr). the cpu cannot read or write the rsr directly. 8.2.2 receive data register (rdr)?'ffdd bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r the rdr stores received data. as each character is received, it is transferred from the rsr to the rdr, enabling the rsr to receive the next character. this double-buffering allows the sci to receive data continuously. the cpu can read but not write the rdr. the rdr is initialized to h'00 at a reset and in the standby modes. 8.2.3 transmit shift register (tsr) bit 7 6 5 4 3 2 1 0 read/write the tsr holds the character currently being transmitted. when transmission of this character is completed, the next character is moved from the transmit data register (tdr) to the tsr and transmission of that character begins. if the tdre bit is still set to ?,?however, nothing is transferred to the tsr. the cpu cannot read or write the tsr directly. 166 8.2.4 transmit data register (tdr)?'ffdb bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the tdr is an 8-bit readable/writable register that holds the next character to be transmitted. when the tsr becomes empty, the character written in the tdr is transferred to the tsr. continuous data transmission is possible by writing the next byte in the tdr while the current byte is being transmitted from the tsr. the tdr is initialized to h'ff at a reset and in the standby modes. 8.2.5 serial mode register (smr)?'ffd8 bit 7 6 5 4 3 2 1 0 c/a chr pe o/e stop mp cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w the smr is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source. it is initialized to h'00 at a reset and in the standby modes. for further information on the smr settings and communication formats, see tables 8-5 and 8-7 in section 8.3, ?peration. bit 7?ommunication mode (c/a): this bit selects the asynchronous or clocked synchronous communication mode. bit 7 c/a description 0 asynchronous communication. (initial value) 1 clocked synchronous communication. 167 bit 6?haracter length (chr): this bit selects the character length in asynchronous mode. it is ignored in synchronous mode. the character length is always eight bits in synchronous mode. bit 6 chr description 0 8 bits per character. (initial value) 1 7 bits per character. (bits 0 to 6 in tdr and rdr are sent and received.) bit 5?arity enable (pe): this bit selects whether to add a parity bit in asynchronous mode. it is ignored in synchronous mode, and when a multiprocessor format is used. bit 5 pe description 0 transmit: no parity bit is added. (initial value) receive: parity is not checked. 1 transmit: a parity bit is added. receive: parity is checked. bit 4?arity mode (o/e ): in asynchronous mode, when parity is enabled (pe = ??, this bit selects even or odd parity. even parity means that a parity bit is added to the data bits for each character to make the total number of 1 s even. odd parity means that the total number of 1 s is made odd. this bit is ignored when pe = ?,?or when a multiprocessor format is used. it is also ignored in the synchronous mode. bit 4 o/e description 0 even parity. (initial value) 1 odd parity. 168 bit 3?top bit length (stop): this bit selects the number of stop bits. it is ignored in the synchronous mode. bit 3 stop description 0 one stop bit (initial value) transmit: one stop bit is added. receive: one stop bit is checked to detect framing errors. 1 two stop bits transmit: two stop bits are added. receive: the first stop bit is checked to detect framing errors; if the second bit is a space (0), it is regarded as the next start bit. bit 2?ultiprocessor mode (mp): this bit selects the multiprocessor format in asynchronous communication. when multiprocessor format is selected, the parity settings of the parity enable bit (pe) and parity mode bit (o/e) are ignored. the mp bit is ignored in synchronous communication. the mp bit is valid only when the mpe bit in the serial/timer control register (stcr) is set to ?. when the mpe bit is cleared to ?,?the multiprocessor communication function is disabled regardless of the setting of the mp bit. bit 2 mp description 0 multiprocessor communication function is disabled. (initial value) 1 multiprocessor communication function is enabled. bits 1 and 0?lock select 1 and 0 (cks1 and cks0): these bits select the internal clock source when the baud rate generator is clocked from within the chip. bit 1 bit 0 cks1 cks0 description 0 0 clock (initial value) 0 1 /4 clock 1 0 /16 clock 1 1 /64 clock 169 8.2.6 serial control register (scr)?'ffda bit 7 6 5 4 3 2 1 0 tie rie te re mpie teie cke1 cke0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w the scr is an 8-bit readable/writable register that enables or disables various sci functions. it is initialized to h'00 at a reset and in the standby modes. bit 7?ransmit interrupt enable (tie): this bit enables or disables the tdr-empty interrupt (txi) requested when the transmit data register empty (tdre) bit in the serial status register (ssr) is set to ?. bit 7 tie description 0 the tdr-empty interrupt request (txi) is disabled. (initial value) 1 the tdr-empty interrupt request (txi) is enabled. bit 6?eceive interrupt enable (rie): this bit enables or disables the receive-end interrupt (rxi) requested when the receive data register full (rdrf) bit in the serial status register (ssr) is set to ?.? it also enables or disables the receive-error interrupt (eri) requested when the overrun error (orer), framing error (fer), or parity error (per) bit is set to ?. bit 6 rie description 0 the receive-end interrupt (rxi) and receive-error interrupt (eri) (initial value) requests are disabled. 1 the receive-end interrupt (rxi) and receive-error interrupt (eri) requests are enabled. 170 bit 5?ransmit enable (te): this bit enables or disables the transmit function. when the transmit function is enabled, the txd pin is automatically used for output. when the transmit function is disabled, the txd pin can be used as a general-purpose i/o port. bit 5 te description 0 the transmit function is disabled. (initial value) the txd pin can be used for general-purpose i/o. 1 the transmit function is enabled. the txd pin is used for output. bit 4?eceive enable (re): this bit enables or disables the receive function. when the receive function is enabled, the rxd pin is automatically used for input. when the receive function is disabled, the rxd pin is available as a general-purpose i/o port. bit 4 re description 0 the receive function is disabled. the rxd pin can be (initial value) used for general-purpose i/o. 1 the receive function is enabled. the rxd pin is used for input. 171 bit 3?ultiprocessor interrupt enable (mpie): when serial data are received in a multiprocessor format, this bit enables or disables the receive-end interrupt (rxi) and receive-error interrupt (eri) until data with the multiprocessor bit set to ??are received. it also enables or disables the transfer of received data from the rsr to the rdr, and enables or disables setting of the rdrf, fer, per, and orer bits in the serial status register (ssr). the mpie bit is ignored when a multiprocessor format is not used, and in synchronous mode. clearing the mpie bit to ??disables the multiprocessor receive interrupt function. in this condition data are received regardless of the value of the multiprocessor bit in the receive data. setting the mpie bit to ??enables the multiprocessor receive interrupt function. in this condition, if the multiprocessor bit in the receive data is ?,?the receive-end interrupt (rxi) and receive-error interrupt (eri) are disabled, the receive data are not transferred from the rsr to the rdr, and the rdrf, fer, per, and orer bits in the serial status register (ssr) are not set. if the multiprocessor bit is ?,?however, the mpb bit in the ssr is set to ?,?the mpie bit is cleared to ?,?the fer, per, and orer bits can be set, and the receive-end and receive-error interrupts are enabled. bit 3 mpie description 0 the multiprocessor receive interrupt function is disabled. (initial value) (normal receive operation) 1 the multiprocessor receive interrupt function is enabled. during the interval before data with the multiprocessor bit set to ??are received, the receive interrupt request (rxi) and receive-error interrupt request (eri) are disabled, the rdrf, fer, per, and orer bits are not set in the serial status register (ssr), and no data are transferred from the rsr to the rdr. the mpie bit is cleared at the following times: (1) when ??is written in mpie. (2) when data with the multiprocessor bit set to ??are received. 172 bit 2?ransmit-end interrupt enable (teie): this bit enables or disables the tsr-empty interrupt (tei) requested when the transmit-end bit (tend) in the serial status register (ssr) is set to ?. bit 2 teie description 0 the tsr-empty interrupt request (tei) is disabled. (initial value) 1 the tsr-empty interrupt request (tei) is enabled. bit 1?lock enable 1 (cke1): this bit selects the internal or external clock source for the baud rate generator. when the external clock source is selected, the sck pin is automatically used for input of the external clock signal. bit 1 cke1 description 0 internal clock source. (initial value) when c/a = ?,?the serial clock signal is output at the sck pin. when c/a = ?,?output depends on the cke0 bit. 1 external clock source. the sck pin is used for input. bit 0?lock enable 0 (cke0): when an internal clock source is used in asynchronous mode, this bit enables or disables serial clock output at the sck pin. this bit is ignored when the external clock is selected, or when synchronous mode is selected. for further information on the communication format and clock source selection, see table 8-7 in section 8.3, ?peration. bit 0 cke0 description 0 the sck pin is not used by the sci (and is available as (initial value) a general-purpose i/o port). 1 the sck pin is used for serial clock output. 173 8.2.7 serial status register (ssr)?'ffdc bit 7 6 5 4 3 2 1 0 tdre rdrf orer fer per tend mpb mpbt initial value 1 0 0 0 0 1 0 0 read/write r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r r r/w note: * software can write a ??to clear the flags, but cannot write a ??in these bits. the ssr is an 8-bit register that indicates transmit and receive status. it is initialized to h'84 at a reset and in the standby modes. bit 7?ransmit data register empty (tdre): this bit indicates when the tdr contents have been transferred to the tsr and the next character can safely be written in the tdr. bit 7 tdre description 0 to clear tdre, the cpu must read tdre after it has been set to ?,? then write a ??in this bit. 1 this bit is set to 1 at the following times: (initial value) (1) when tdr contents are transferred to the tsr. (2) when the te bit in the scr is cleared to ?. bit 6?eceive data register full (rdrf): this bit indicates when one character has been received and transferred to the rdr. bit 6 rdrf description 0 to clear rdrf, the cpu must read rdrf after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 when one character is received without error and transferred from the rsr to the rdr. 174 bit 5?verrun error (orer): this bit indicates an overrun error during reception. bit 5 orer description 0 to clear orer, the cpu must read orer after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 if reception of the next character ends while the receive data register is still full (rdrf = ??. bit 4?raming error (fer): this bit indicates a framing error during data reception in asynchronous mode. it has no meaning in synchronous mode. bit 4 fer description 0 to clear fer, the cpu must read fer after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 if a framing error occurs (stop bit = ??. bit 3?arity error (per): this bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. this bit has no meaning in the synchronous mode, or when a communication format without parity bits is used. bit 3 per description 0 to clear per, the cpu must read per after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to ??when a parity error occurs (the parity of the received data does not match the parity selected by the o/e bit in smr). 175 bit 2?ransmit end (tend): this bit indicates that transmission of a character has ended and the serial communication interface has stopped transmitting because there is no valid data in the tdr. the tend bit is also set to ??when the te bit in the serial control register (scr) is cleared to ?. the tend bit can be read but not written. to use the tei interrupt, after tend is cleared to ? at the start of data transmission, set teie to ??to enable the interrupt. bit 2 tend description 0 to clear tend, the cpu must read tdre after (initial value) it has been set to ?,?then write a ??in tdre. 1 this bit is set to ??when: (1) te = ? (2) tdre = ??at the end of transmission of a character bit 1?ultiprocessor bit (mpb): stores the value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode. in synchronous mode, when a multiprocessor format is not used, or if the re bit is cleared to ??when a multiprocessor format is used, the mpb bit retains its previous value. mpb can be read but not written. bit 1 mpb description 0 multiprocessor bit = ??in receive data. (initial value) 1 multiprocessor bit = ??in receive data. bit 0?ultiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit inserted in transmit data when a multiprocessor format is used in asynchronous communication mode. the mpbt bit is double-buffered, in the same way that tsr and tdr are double-buffered. the mpbt bit has no effect in synchronous mode, or when a multiprocessor format is not used. bit 0 mpbt description 0 multiprocessor bit = ??in transmit data. (initial value) 1 multiprocessor bit = ??in transmit data. 176 8.2.8 bit rate register (brr)?'ffd9 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the brr is an 8-bit register that, together with the cks1 and cks0 bits in the smr, determines the baud rate output by the baud rate generator. the brr is initialized to h'ff (the slowest rate) at a reset and in the standby modes. tables 8-3 and 8-4 show examples of brr (n) and cks (n) settings for commonly used bit rates. table 8-3. examples of brr settings in asynchronous mode (1) xtal frequency (mhz) 2 2.4576 4 4.194304 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 ?.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 ?.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 0 7 0 0 12 +0.16 0 13 ?.48 9600 0 3 0 0 6 ?.48 19200 0 1 0 31250 0 0 0 0 1 0 38400 0 0 0 177 table 8-3. examples of brr settings in asynchronous mode (2) xtal frequency (mhz) 4.9152 6 7.3728 8 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 1 174 ?.26 2 52 +0.50 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 ?.34 0 23 0 0 25 +0.16 9600 0 7 0 0 9 ?.34 0 11 0 0 12 +0.16 19200 0 3 0 0 4 ?.34 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 table 8-3. examples of brr settings in asynchronous mode (3) xtal frequency (mhz) 9.8304 10 12 12.288 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 2 86 +0.31 2 88 ?.25 2 106 ?.44 2 108 +0.08 150 1 255 0 2 64 +0.16 2 77 0 2 79 0 300 1 127 0 1 129 +0.16 1 155 0 1 159 0 600 0 255 0 1 64 +0.16 1 77 0 1 79 0 1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0 2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0 4800 0 31 0 0 32 ?.36 0 38 +0.16 0 39 0 9600 0 15 0 0 15 +1.73 0 19 ?.34 0 19 0 19200 0 7 0 0 7 +1.73 0 4 0 31250 0 4 ?.70 0 4 0 0 5 0 0 5 +2.40 38400 0 3 0 0 3 +1.73 178 table 8-3. examples of brr settings in asynchronous mode (4) xtal frequency (mhz) 14.7456 16 19.6608 20 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 2 130 ?.07 2 141 +0.03 2 174 ?.26 3 43 +0.88 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16 4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16 9600 0 23 0 0 25 +0.16 0 31 0 0 32 ?.36 19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73 31250 0 7 0 0 9 ?.70 0 9 0 38400 0 5 0 0 7 0 0 7 +1.73 note: if possible, the error should be within 1%. b = osc ? 10 6 /[64 ? 2 2n ? (n + 1)] n : brr value (0 n 255) osc : crystal oscillator frequency in mhz b : bit rate (bits/second) n : internal clock source (0, 1, 2, or 3) the meaning of n is given by the table below: n cks1 cks0 clock 0 0 0 1 0 1 /4 2 1 0 /16 3 1 1 /64 179 table 8-4. examples of brr settings in synchronous mode xtal frequency (mhz) bit 2 4 8 10 16 20 rate n n n n n n n n n n n n 100 250 1 249 2 124 2 249 3 124 500 1 124 1 249 2 124 2 249 1k 0 249 1 124 1 249 2 124 2.5k 0 99 0 199 1 99 1 124 1 199 1 249 5k 0 49 0 99 0 199 0 249 1 99 1 124 10k 0 24 0 49 0 99 0 124 0 199 0 249 25k 0 9 0 19 0 39 0 49 0 79 0 99 50k 0 4 0 9 0 19 0 24 0 39 0 49 100k 0 4 0 9 0 19 0 24 250k 0 0* 0 1 0 3 0 4 0 7 0 9 500k 0 0* 0 1 0 3 0 4 1m 0 0* 0 1 2.5m 0 0* notes: blank: no setting is available. ? a setting is available, but the bit rate is inaccurate. * continuous transfer is not possible. b = osc ? 10 6 /[8 2 2n (n + 1)] n : brr value (0 n 255) osc : crystal oscillator frequency in mhz b : bit rate (bits/second) n : internal clock source (0, 1, 2, or 3) the meaning of n is given by the table below: n cks1 cks0 clock 0 0 0 1 0 1 /4 2 1 0 /16 3 1 1 /64 180 8.2.9 serial/timer control register (stcr)?'ffc3 bit 7 6 5 4 3 2 1 0 mpe icks1 icks0 initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w the stcr is an 8-bit readable/writable register that controls the operating mode of the serial communication interface and selects input clock sources for the 8-bit timer counters (tcnt). the stcr is initialized to h'f8 by a reset. bits 7 to 3?eserved: these bits cannot be modified and are always read as ?. bit 2?ultiprocessor enable (mpe): enables or disables the sci s multiprocessor communication function. bit 2 mpe description 0 the multiprocessor communication function is disabled, (initial value) regardless of the setting of the mp bit in smr. 1 the multiprocessor communication function is enabled. the multi- processor format can be selected by setting the mp bit in smr to ?. bits 1 and 0?nternal clock source select 1 and 0 (icks1, icks0): these bits select the clock input to the timer counters (tcnt) in the 8-bit timers. for further information see section 7.2.3, ?imer control register. 181 8.3 operation 8.3.1 overview the sci supports serial data transfer in two modes. in asynchronous mode each character is synchronized individually. in synchronous mode communication is synchronized with a clock signal. the selection of asynchronous or synchronous mode and the communication format depend on settings in the smr as indicated in table 8-5. the clock source depends on the settings of the c/a bit in the smr and the cke1 and cke0 bits in the scr as indicated in table 8-6. (1) asynchronous mode: data lengths of seven or eight bits can be selected. a parity bit or multiprocessor bit can be added, and stop bit lengths of one or two bits can be selected. these selections determine the communication format and character length. framing errors (fer), parity errors (per) and overrun errors (orer) can be detected in receive data, and the line-break condition can be detected. an internal or external clock source can be selected for the serial clock. when an internal clock source is selected, the sci is clocked by the on-chip baud rate generator and can output a clock signal at the bit-rate frequency. when the external clock source is selected, the on-chip baud rate generator is not used. the external clock frequency must be 16 times the bit rate. (2) synchronous mode: the transmit data length is eight bits. overrun errors (orer) can be detected in receive data. an internal or external clock source can be selected for the serial clock. when an internal clock source is selected, the sci is clocked by the on-chip baud rate generator and outputs a serial clock signal. when the external clock source is selected, the on-chip baud rate generator is not used and the sci operates on the input serial clock. 182 table 8-5. communication formats used by sci smr settings communication format bit 7 bit 6 bit 2 bit 5 bit 3 data multipro- parity stop-bit c/a chr mp pe stop mode length cessor bit bit length 0 0 0 0 0 asynchronous mode 8 bits none none 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 1 0 0 7 bits none 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 0 1 0 asynchronous mode 8 bits present none 1 bit 1 (multiprocessor 2 bits 1 0 format) 7 bits 1 bit 1 2 bits 1 synchronous mode 8 bits none none table 8-6. sci clock source selection smr scr bit 7 bit 1 bit 0 serial transmit/receive clock c/a cke1 cke0 mode clock source sck pin function 0 0 0 async internal input/output port (not used by sci) 1 serial clock output at bit rate 1 0 external serial clock input at 16 bit rate 1 1 0 0 sync internal serial clock output 1 1 0 external serial clock input 1 183 8.3.2 asynchronous mode in asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. full duplex data transfer is possible because the sci has independent transmit and receive sections. double buffering in both sections enables data to be written and read during serial communication, for continuous data transfer. figure 8-2 shows the general format of one character sent or received in asynchronous mode. the communication channel is normally held in the mark state (high). character transmission or reception starts with a transition to the space state (low). the first bit transmitted or received is the start bit (low). it is followed by the data bits, in which the least significant bit (lsb) comes first. the data bits are followed by the parity or multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame. in receiving, the sci synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). figure 8-2. data format in asynchronous mode (1) data format: table 8-7 lists the data formats that can be sent and received in asynchronous mode. twelve formats can be selected by bits in the smr. d0 d1 d7 start bit 1 bit 7 or 8 bits one unit of data (one character or frame) parity or multipro- cessor bit stop bit 0 or 1 bit 1 or 2 bits idle state (mark) (lsb) (msb) serial data fig. 8-2 184 table 8-7. data formats in asynchronous mode notes: smr: serial mode register start: start bit stop: stop bit p: parity bit mpb: multiprocessor bit (2) clock: in asynchronous mode it is possible to select either an internal clock created by the on- chip baud rate generator, or an external clock input at the sck pin. the clock selection depends on the c/a bit in the serial mode register (smr) and the cke0 and cke1 bits in the serial control register (scr). refer to table 8-6. if an external clock is input at the sck pin, its frequency should be 16 times the desired bit rate. if the internal clock provided by the on-chip baud rate generator is selected and the sck pin is used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the center of the transmit data bits. figure 8-3 shows the phase relationship between the output clock and transmit data. chr 0 0 0 0 1 1 1 1 0 0 1 1 pe 0 0 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr bits 1 2 3 4 5 6 7 8 9 10 11 12 s s s s s s s s s s s s 8-bit data stop 8-bit data stop stop 8-bit data p stop 8-bit data p stop stop 7-bit data stop 7-bit data stop stop 7-bit data p stop 7-bit data p stop stop 8-bit data mpb stop 8-bit data mpb stop stop 7-bit data mpb stop 7-bit data mpb stop stop 185 figure 8-3. phase relationship between clock output and transmit data (asynchronous mode) (3) transmitting and receiving data ? sci initialization: before transmitting or receiving, software must clear the te and re bits to ??in the serial control register (scr), then initialize the sci as follows. note: when changing the communication mode or format, always clear the te and re bits to ? before following the procedure given below. clearing te to ??sets tdre to ??and initializes the transmit shift register (tsr). clearing re to ?,?however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr), which retain their previous contents. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. sci operation becomes unreliable if the clock is stopped. ? d0 d1 d2 d3 d4 d5 d6 d7 0/1 ? ? one frame h8/329 u.m. '92 fig. 8-3 186 figure 8-4. sample flowchart for sci initialization clear te and re bits to ??in scr 1 bit interval elapsed? start transmitting or receiving no yes 1. select the communication format in the serial mode register (smr). 2. write the value corresponding to the bit rate in the bit rate register (brr). this step is not necessary when an external clock is used. 3. select interrupts and the clock source in the serial control register (scr). leave te and re cleared to ?.?if clock output is selected, in asynchronous mode, clock output starts immediately after the setting is made in scr. 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr). setting te or re enables the sci to use the txd or rxd pin. also set the rie, tie, teie, and mpie bits as necessary to enable interrupts. the initial states are the mark transmit state, and the idle receive state (waiting for a start bit). h8/338 u.m. '92 fig. 9-4 select communication format in smr 1 set value in brr 2 set cke1 and cke0 bits in scr (leaving te and re cleared to ?? 3 set te or re to ??in scr, and set rie, tie, teie, and mpie as necessary 4 initialization 187 ? transmitting serial data: follow the procedure below for transmitting serial data. figure 8-5. sample flowchart for transmitting serial data start transmitting read tdre bit in ssr tdre = ?? write transmit data in tdr end of transmission? end 1 2 3 no yes no yes sci initialization: the transmit data output function of the txd pin is selected automatically. (a) (b) to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if tdre = ?,?write data in tdr, then clear tdre to ?. to end serial transmission: end of transmission can be confirmed by checking transition of the tend bit from ??to ?.? this can be reported by a tei interrupt. to output a break signal at the end of serial transmission: set the ddr bit to ??and clear the dr bit to ??(ddr and dr are i/o port registers), then clear te to ??in scr. h8/338 u.m. '92 fig. 9-5 if using multiprocessor format, select mpbt value in ssr clear tdre bit to ??in ssr read tend bit in ssr tend = ?? no yes output break signal? no yes clear te bit in scr to ? 4 sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is ?,?then write transmit data in the transmit data register (tdr) and clear tdre to ?.? if a multiprocessor format is selected, after writing the transmit data write ??or ??in the multiprocessor bit transfer (mpbt) in ssr. transition of the tdre bit from ??to ??can be reported by an interrupt. 1. 3. 4. 2. initialize set dr = ?,?ddr = ? serial transmission 188 in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to ??the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). 2. after loading the data from tdr into tsr, the sci sets the tdre bit to ??and starts transmitting. if the tie bit (tdr-empty interrupt enable) is set to ??in scr, the sci requests a txi interrupt (tdr-empty interrupt) at this time. serial transmit data are transmitted in the following order from the txd pin: (a) start bit: one ??bit is output. (b) transmit data: seven or eight bits are output, lsb first. (c) parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. (d) stop bit: one or two ??bits (stop bits) are output. (e) mark state: output of ??bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is ?,?the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is ?,?the sci sets the tend bit to ??in ssr, outputs the stop bit, then continues output of ??bits in the mark state. if the teie bit (tsr-empty interrupt enable) in scr is set to ?,?a tei interrupt (tsr-empty interrupt) is requested. 189 figure 8-6 shows an example of sci transmit operation in asynchronous mode. figure 8-6. example of sci transmit operation (8-bit data with parity and one stop bit) ? start bit ? d0 d1 d7 0/1 stop bit ? data parity bit start bit ? d0 d1 d7 0/1 stop bit ? data parity bit ? mark (idle) state tdre tend txi request txi interrupt handler writes data in tdr and clears tdre to ? txi request 1 frame tei request h8/329 u.m. '92 fig. 8-6 190 ? receiving serial data: follow the procedure below for receiving serial data. figure 8-7. sample flowchart for receiving serial data start receiving read rdrf bit in ssr rdrf = ?? read receive data from rdr, and clear rdrf bit to ? in ssr per rer orer = ?? clear re to ??in scr finished receiving? end error handling start error handling fer = ?? clear error flags to ??in scr return break? clear re to ? in scr end 1 2 no yes yes no no yes 4 1. sci initialization: the receive data function of the rxd pin is selected automatically. 2. sci status check and receive data read: read the serial status register (ssr), check that rdrf is set to ?,?then read receive data from the receive data register (rdr) and clear rdrf to ?.? transition of the rdrf bit from ??to ??can be reported by an rxi interrupt. 4. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer bits in ssr to identify the error. after executing the necessary error handling, clear orer, per, and fer all to ?.? transmitting and receiving cannot resume if orer, per, or fer remains set to ?.? when a framing error occurs, the rxd pin can be read to detect the break state. yes no yes no h8/338 u.m. '92 fig. 9-7 read orer, per, and fer in ssr 3 3. to continue receiving serial data: read rdr and clear rdrf to 0 before the stop bit of the current frame is received. initialize 191 in receiving, the sci operates as follows. 1. the sci monitors the receive data line and synchronizes internally when it detects a start bit. 2. receive data are shifted into rsr in order from lsb to msb. 3. the parity bit and stop bit are received. after receiving these bits, the sci makes the following checks: (a) parity check: the number of 1s in the receive data must match the even or odd parity setting of the o/e bit in smr. (b) stop bit check: the stop bit value must be ?.? if there are two stop bits, only the first stop bit is checked. (c) status check: rdrf must be ??so that receive data can be loaded from rsr into rdr. if these checks all pass, the sci sets rdrf to ??and stores the received data in rdr. if one of the checks fails (receive error), the sci operates as indicated in table 8-8. note: when a receive error flag is set, further receiving is disabled. the rdrf bit is not set to ?. be sure to clear the error flags. 4. after setting rdrf to ?,?if the rie bit (receive-end interrupt enable) is set to ??in scr, the sci requests an rxi (receive-end) interrupt. if one of the error flags (orer, per, or fer) is set to ??and the rie bit in scr is also set to ?,?the sci requests an eri (receive-error) interrupt. 192 figure 8-8 shows an example of sci receive operation in asynchronous mode. table 8-8. receive error conditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends receive data not loaded from while rdrf is still set to ?? rsr into rdr in ssr framing error fer stop bit is ? receive data loaded from rsr into rdr parity error per parity of receive data differs receive data loaded from rsr from even/odd parity setting into rdr in smr figure 8-8. example of sci receive operation (8-bit data with parity and one stop bit) ? start bit ? d0 d1 d7 0/1 stop bit ? data parity bit start bit ? d0 d1 d7 0/1 stop bit ? data parity bit ? mark (idle) state rdrf fer rxi request 1 frame framing error, eri request h8/329 u.m. '92 fig. 8-8 rxi interrupt handler reads data in rdr and clears rdrf to ? 193 (4) multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id. a serial communication cycle consists of two cycles: an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to ?.? next the transmitting processor sends transmit data with the multiprocessor bit cleared to ?. receiving processors skip incoming data until they receive data with the multiprocessor bit set to ?. after receiving data with the multiprocessor bit set to ?,?the receiving processor with an id matching the received data continues to receive further incoming data. multiple processors can send and receive data in this way. four formats are available. parity-bit settings are ignored when a multiprocessor format is selected. for details see table 8-7. figure 8-9. example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a) transmitting processor receiving processor a serial communication line receiving processor b receiving processor c receiving processor d (id = 01) (id = 02) (id = 03) (id = 04) serial data h'01 h'aa (mpb = 1) (mpb = 0) id-sending cycle: receiving processor address data-sending cycle: data sent to receiving processor specified by id h8/329 u.m. '92 fig. 8-9 mpb: multiprocessor bit 194 ? transmitting multiprocessor serial data: see figures 8-5 and 8-6. ? receiving multiprocessor serial data: follow the procedure below for receiving multiprocessor serial data. figure 8-10. sample flowchart for receiving multiprocessor serial data start receiving set mpie bit to ??in scr read rdrf bit in ssr rdrf = ?? read receive data from rdr own id? read orer and fer bits in ssr fer orer = ?? read rdrf bit in ssr rdrf = 1? read orer and fer bits in ssr read receive data from rdr fer + orer = 1? finished receiving? clear re to 0 in scr end error handling fer = 1? clear error flags return break? clear re bit to 0 in scr end 1 2 3 4 no yes no yes yes no no yes yes no no yes 5 1. sci initialization: the receive data function of the rxd pin is selected automatically. 2. id receive cycle: set the mpie bit in the serial control register (scr) to 1. 3. sci status check and id check: read the serial status register (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and compare with the processor?s own id. transition of the rdrf bit from 0 to 1 can be reported by an rxi interrupt. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. 4. sci status check and data receiving: read ssr, check that rdrf is set to 1, then read data from the receive data register (rdr) and write 0 in the rdrf bit. transition of the rdrf bit from 0 to 1 can be reported by an rxi interrupt. 5. receive error handling and break detection: if a receive error occurs, read the orer and fer bits in ssr to identify the error. after executing the necessary error handling, clear both orer and fer to 0. receiving cannot resume while orer or fer remains set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. yes no yes no h8/338 u.m. '92 fig. 9-10 initialize start error handling 195 figure 8-11 shows an example of sci receive operation using a multiprocessor format. figure 8-11. example of sci receive operation (eight-bit data with multiprocessor bit and one stop bit) ? start bit ? d0 d1 d7 ? stop bit ? data (id1) mpb start bit ? d0 d1 d7 ? stop bit ? data (data2) mpb ? mark (idle) state mpie rdrf h8/329 u.m. '92 fig. 8-11 rdr value id1 rxi request, mpie = ? rxi handler reads rdr data and clears rdrf to ? not own id, so mpie is set to ??again no rxi request, rdr not updated (multiprocessor interrupt) (a) own id does not match data ? start bit ? d0 d1 d7 ? stop bit ? data (id2) mpb start bit ? d0 d1 d7 ? stop bit ? data (data2) mpb ? mark (idle) state mpie rdrf rdr value id2 rxi request, mpie = ? rxi handler reads rdr data and clears rdrf to ? own id, so receiving continues, with data received at each rxi mpie set to ??again (multiprocessor interrupt) (b) own id matches data id1 data 2 196 8.3.3 clocked synchronous operation (1) overview: in clocked synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. the transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 8-12 shows the general format in clocked synchronous serial communication. figure 8-12. data format in clocked synchronous communication in clocked synchronous serial communication, each data bit is sent on the communication line from one falling edge of the serial clock to the next. data are received in synchronization with the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from lsb (first) to msb (last). after output of the msb, the communication line remains in the state of the msb until the next falling edge of the serial clock. serial clock data bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb msb don? care don? care h8/329 u.m. '92 fig. 8-12 one unit (character or frame) of serial data * * note: high except in continuous transmitting or receiving * 197 ? communication format: the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added. ? clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected by clearing or setting the cke1 bit in the serial control register (scr). see table 8-5. when the sci operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains at the high level. (2) transmitting and receiving data ? sci initialization: the sci must be initialized in the same way as in asynchronous mode. see figure 8-4. when switching from asynchronous mode to clocked synchronous mode, check that the orer, fer, and per bits are cleared to ?.? transmitting and receiving cannot begin if orer, fer, or per is set to ?. 198 ? transmitting serial data: follow the procedure below for transmitting serial data. figure 8-13. sample flowchart for serial transmitting start transmitting read tdre bit in ssr tdre = ?? write transmit data in tdr and clear tdre bit to ??in ssr end of transmission? end 1 2 3 no yes no yes sci initialization: the transmit data output function of the txd pin is selected automatically. (a) (b) to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if tdre = ?,?write data in tdr, then clear tdre to ?. to end serial transmission: end of transmission can be confirmed by checking transition of the tend bit from ??to ?.? this can be reported by a tei interrupt. h8/338 u.m. '92 fig. 9-13 read tend bit in ssr tend = ?? no yes sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is ?,?then write transmit data in the transmit data register (tdr) and clear tdre to ?.? transition of the tdre bit from ??to ??can be reported by a txi interrupt. 1. 3. 2. initialize clear te bit to ??in scr serial transmission 199 in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to ??the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). 2. after loading the data from tdr into tsr, the sci sets the tdre bit to ??and starts transmitting. if the tie bit (tdr-empty interrupt enable) in scr is set to ?,?the sci requests a txi interrupt (tdr-empty interrupt) at this time. if clock output is selected the sci outputs eight serial clock pulses, triggered by the clearing of the tdre bit to ?.? if an external clock source is selected, the sci outputs data in synchronization with the input clock. data are output from the txd pin in order from lsb (bit 0) to msb (bit 7). 3. the sci checks the tdre bit when it outputs the msb (bit 7). if tdre is ?,?the sci loads data from tdr into tsr, then begins serial transmission of the next frame. if tdre is ?,?the sci sets the tend bit in ssr to ?,?transmits the msb, then holds the output in the msb state. if the teie bit (transmit-end interrupt enable) in scr is set to ?,?a tei interrupt (tsr- empty interrupt) is requested at this time. 4. after the end of serial transmission, the sck pin is held at the high level. 200 figure 8-14 shows an example of sci transmit operation. figure 8-14. example of sci transmit operation serial clock data bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 h8/329 u.m. '92 fig. 8-14 txi request tdre tend txi interrupt handler writes data in tdr and clears tdre to ? txi request tei request 1 frame 201 ? receiving serial data: follow the procedure below for receiving serial data. when switching from asynchronous mode to clocked synchronous mode, be sure to check that per and fer are cleared to ?.? if per or fer is set to ??the rdrf bit will not be set and both transmitting and receiving will be disabled. figure 8-15. sample flowchart for serial receiving start receiving read rdrf bit in ssr rdrf = ?? read receive data from rdr, and clear rdrf bit to ??in ssr orer = ?? read orer in ssr finished receiving? clear re to ??in scr end error handling 1 2 3 no yes yes no no yes 4 1. sci initialization: the receive data function of the rxd pin is selected automatically. 3. to continue receiving serial data: read rdr and clear rdrf to ??before the msb (bit 7) of the current frame is received. 4. receive error handling: if a receive error occurs, read the orer bit in ssr then, after executing the necessary error handling, clear orer to ?.? neither transmitting nor receiving can resume while orer remains set to ?.? when clock output mode is selected, receiving can be halted temporarily by receiving one dummy byte and causing an overrun error. when preparations to receive the next data are completed, clear the orer bit to ?.? this causes receiving to resume, so h8/338 u.m. '92 fig. 9-15 clear orer to ??in ssr return overrun error handling 2. sci status check and receive data read: read the serial status register (ssr), check that rdrf is set to ?,?then read receive data from the receive data register (rdr) and clear rdrf to ?.? transition of the rdrf bit from ??to ??can be reported by an rxi interrupt. return to the step marked 2 in the flowchart. start error handling initialize 202 in receiving, the sci operates as follows. 1. if an external clock is selected, data are input in synchronization with the input clock. if clock output is selected, as soon as the re bit is set to ??the sci begins outputting the serial clock and inputting data. if clock output is stopped because the orer bit is set to ?,?output of the serial clock and input of data resume as soon as the orer bit is cleared to ?. 2. receive data are shifted into rsr in order from lsb to msb. after receiving the data, the sci checks that rdrf is ??so that receive data can be loaded from rsr into rdr. if this check passes, the sci sets rdrf to ??and stores the received data in rdr. if the check does not pass (receive error), the sci operates as indicated in table 8-8. note: both transmitting and receiving are disabled while a receive error flag is set. the rdrf bit is not set to ?.? be sure to clear the error flag. 3. after setting rdrf to ?,?if the rie bit (receive-end interrupt enable) is set to ??in scr, the sci requests an rxi (receive-end) interrupt. if the orer bit is set to ??and the rie bit in scr is set to ?,?the sci requests an eri (receive-error) interrupt. when clock output mode is selected, clock output stops when the re bit is cleared to ??or the orer bit is set to ?.? to prevent clock count errors, it is safest to receive one dummy byte and generate an overrun error. 203 figure 8-16 shows an example of sci receive operation. figure 8-16. example of sci receive operation serial clock data bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 h8/329 u.m. '92 fig. 8-16 rxi request rdrf orer rxi interrupt handler reads data in rdr and clears rdrf to ? rxi request overrun error, eri request 1 frame 204 ? transmitting and receiving serial data simultaneously: follow the procedure below for transmitting and receiving serial data simultaneously. if clock output mode is selected, output of the serial clock begins simultaneously with serial transmission. figure 8-17. sample flowchart for serial transmitting and receiving note: in switching from transmitting or receiving to simultaneous transmitting and receiving, clear both te and re to ?,?then set both te and re to ?. read tdre bit in ssr tdre = ?? write transmit data in tdr and clear tdre bit to ??in ssr orer = ?? read rdrf bit in ssr end of transmitting and receiv- ing? clear te and re bits to ??in scr end error handling 1 2 3 no yes yes no no yes 5 1. sci initialization: the transmit data output function of the txd pin and receive data input function of the rxd pin are selected, enabling simultaneous transmitting and receiving. 4. to continue transmitting and receiving serial data: read rdr and clear rdrf to ??before the msb (bit 7) of the current frame is received. also read the tdre bit and check that it is set to ?,?indicating that it is safe to write; then write data in tdr and clear tdre to ??before the msb (bit 7) of the current frame is transmitted. h8/329 u.m. '92 fig. 8-17 2. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is ?,?then write transmit data in the transmit data register (tdr) and clear tdre to ?.? transition of the tdre bit from ??to ??can be reported by a txi interrupt. rdrf = ?? read receive data from rdr and clear rdrf bit to ??in ssr read orer bit in ssr 4 no yes 3. sci status check and receive data read: read the serial status register (ssr), check that the rdrf bit is ?,?then read receive data from the receive data register (rdr) and clear rdrf to ?.? transition of the rdrf bit from ??to ??can be reported by an rxi interrupt. 5. receive error handling: if a receive error occurs, read the orer bit in ssr then, after executing the necessary error handling, clear orer to ?.? neither transmitting nor receiving can resume while orer remains set to ?. initialize start 205 8.4 sci interrupts the sci can request four types of interrupts: eri, rxi, txi, and tei. table 8-9 indicates the source and priority of these interrupts. the interrupt sources can be enabled or disabled by the tie, rie, and teie bits in the scr. independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (eri) is the logical or of three sources: overrun error, framing error, and parity error. the txi interrupt indicates that the next transmit data can be written. the tei interrupt indicates that the sci has stopped transmitting data. table 8-9. sci interrupt sources interrupt description priority eri receive-error interrupt (orer, fer, or per) high rxi receive-end interrupt (rdrf) txi tdr-empty interrupt (tdre) tei tsr-empty interrupt (tend) low 8.5 application notes application programmers should note the following features of the sci. (1) tdr write: the tdre bit in the ssr is simply a flag that indicates that the tdr contents have been transferred to the tsr. the tdr contents can be rewritten regardless of the tdre value. if a new byte is written in the tdr while the tdre bit is ?,?before the old tdr contents have been moved into the tsr, the old byte will be lost. software should check that the tdre bit is set to ??before writing to the tdr. 206 (2) multiple receive errors: table 8-10 lists the values of flag bits in the ssr when multiple receive errors occur, and indicates whether the rsr contents are transferred to the rdr. table 8-10. ssr bit states and data transfer when multiple receive errors occur ssr bits rsr receive error rdrf orer fer per rdr *2 overrun error 1 *1 1 0 0 no framing error 0 0 1 0 yes parity error 0 0 0 1 yes overrun and framing errors 1 *1 1 1 0 no overrun and parity errors 1 *1 1 0 1 no framing and parity errors 0 0 1 1 yes overrun, framing, and parity errors 1 *1 1 1 1 no notes: *1 set to ??before the overrun error occurs. *2 yes: the rsr contents are transferred to the rdr. no: the rsr contents are not transferred to the rdr. (3) line break detection: when the rxd pin receives a continuous stream of 0 s in asynchronous mode (line-break state), a framing error occurs because the sci detects a ??stop bit. the value h'00 is transferred from the rsr to the rdr. software can detect the line-break state as a framing error accompanied by h'00 data in the rdr. the sci continues to receive data, so if the fer bit is cleared to ??another framing error will occur. (4) sampling timing and receive margin in asynchronous mode: the serial clock used by the sci in asynchronous mode runs at 16 times the baud rate. the falling edge of the start bit is detected by sampling the rxd input on the falling edge of this clock. after the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. see figure 8-18. it follows that the receive margin can be calculated as in equation (1). when the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). this is a theoretical limit, however. in practice, system designers should allow a margin of 20% to 30%. 207 figure 8-18. sampling timing (asynchronous mode) m = {(0.5 ?1/2n) ?(d ?0.5)/n ?(l ?0.5)f} ? 100 [%] (1) m : receive margin n : ratio of basic clock to baud rate (n=16) d : duty factor of clock?atio of high pulse width to low width (0.5 to 1.0) l : frame length (9 to 12) f : absolute clock frequency deviation when d = 0.5 and f = 0 m = (0.5 ?/2 ? 16) ? 100 [%] = 46.875% (2) 1 2 4 0 5 6 7 8 9 3 2 1 2 3 4 5 6 7 8 9 1 1 1 1 2 1 3 1 4 1 5 1 6 1 0 1 3 1 4 1 5 1 6 1 2 1 0 1 1 3 4 5 basic clock sync sampling data sampling d0 d1 receive data start bit ?.5 pulses +7.5 pulses figure 8-18 208 section 9. a/d converter 9.1 overview the h8/329 series includes an analog-to-digital converter module with eight input channels. a/d conversion is performed by the successive approximations method with 8-bit resolution. 9.1.1 features the features of the on-chip a/d module are: 8-bit resolution eight analog input channels rapid conversion conversion time is 12.2 s per channel (minimum) with a 10mhz system clock external triggering can be selected single and scan modes single mode: a/d conversion is performed once. scan mode: a/d conversion is performed in a repeated cycle on one to four channels. sample-and-hold function four 8-bit data registers these registers store a/d conversion results for up to four channels. a cpu interrupt (adi) can be requested at the completion of each a/d conversion cycle. 209 9.1.2 block diagram figure 9-1. block diagram of a/d converter module data bus internal data bus successive approximations register a d d r a a d d r b a d d r c a d d r d a d c s r a d c r analog multi- plexer + comparator sample and hold circuit interrupt signal /8 /16 bus interface adtrg adi 8 bit d/a control circuit an 0 an 2 an 1 an 3 an 4 an 5 an 6 an 7 av cc av ss figure 9-1 adcr: a/d control register (8 bits) adcsr: a/d control/status register (8 bits) addra: a/d data register a (8 bits) addrb: a/d data register b (8 bits) addrc: a/d data register c (8 bits) addrd: a/d data register d (8 bits) 210 9.1.3 input pins table 9-1 lists the input pins used by the a/d converter module. the eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (an 0 to an 3 ) and analog inputs 4 to 7 (an 4 to an 7 ), respectively. table 9-1. a/d input pins name abbreviation i/o function analog supply voltage av cc input power supply and reference voltage for the analog circuits. analog ground av ss input ground and reference voltage for the analog circuits. analog input 0 an 0 input analog input 1 an 1 input analog input pins, group 0 analog input 2 an 2 input analog input 3 an 3 input analog input 4 an 4 input analog input 5 an 5 input analog input pins, group 1 analog input 6 an 6 input analog input 7 an 7 input a/d external trigger adtrg input external trigger for starting a/d conversion 9.1.4 register configuration table 9-2 lists the registers of the a/d converter module. table 9-2. a/d registers name abbreviation r/w initial value address a/d data register a addra r h'00 h'ffe0 a/d data register b addrb r h'00 h'ffe2 a/d data register c addrc r h'00 h'ffe4 a/d data register d addrd r h'00 h'ffe6 a/d control/status register adcsr r/(w)* h'00 h'ffe8 a/d control register adcr r/w h'7e h'ffea note: * software can write a ??to clear bit 7, but cannot write a ??in this bit. 211 9.2 register descriptions 9.2.1 a/d data registers (addr)?'ffe0 to h'ffe6 bit 7 6 5 4 3 2 1 0 addrn initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r (n = a to d) the four a/d data registers (addra to addrd) are 8-bit read-only registers that store the results of a/d conversion. each data register is assigned to two analog input channels as indicated in table 9-3. the a/d data registers are always readable by the cpu. the a/d data registers are initialized to h'00 at a reset and in the standby modes. table 9-3. assignment of data registers to analog input channels analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd 9.2.2 a/d control/status register (adcsr)?'ffe8 bit 7 6 5 4 3 2 1 0 adf adie adst scan cks ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 read/write r/(w)* r/w r/w r/w r/w r/w r/w r/w note: * software can write a ??in bit 7 to clear the flag, but cannot write a ??in this bit. the a/d control/status register (adcsr) is an 8-bit readable/writable register that controls the operation of the a/d converter module. 212 the adcsr is initialized to h'00 at a reset and in the standby modes. bit 7?/d end flag (adf): this status flag indicates the end of one cycle of a/d conversion. bit 7 adf description 0 to clear adf, the cpu must read adf after (initial value) it has been set to ?,?then write a ??in this bit. 1 this bit is set to 1 at the following times: (1) single mode: when one a/d conversion is completed. (2) scan mode: when inputs on all selected channels have been converted. bit 6?/d interrupt enable (adie): this bit selects whether to request an a/d interrupt (adi) when a/d conversion is completed. bit 6 adie description 0 the a/d interrupt request (adi) is disabled. (initial value) 1 the a/d interrupt request (adi) is enabled. bit 5?/d start (adst): the a/d converter operates while this bit is set to ?.? this bit can be set to ??by the external trigger signal adtrg. bit 5 adst description 0 a/d conversion is halted. (initial value) 1 (1) single mode: one a/d conversion is performed. the adst bit is automatically cleared to ??at the end of the conversion. (2) scan mode: a/d conversion starts and continues cyclically on the selected channels until the adst bit is cleared to ??by software (or a reset, or by entry to a standby mode). 213 bit 4?can mode (scan): this bit selects the scan mode or single mode of operation. see section 9.3, ?peration?for descriptions of these modes. the mode should be changed only when the adst bit is cleared to ?. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3?lock select (cks): this bit controls the a/d conversion time. the conversion time should be changed only when the adst bit is cleared to ?. bit 3 cks description 0 conversion time = 242 states (max) (initial value) 1 conversion time = 122 states (max) bits 2 to 0?hannel select 2 to 0 (ch2 to ch0): these bits and the scan bit combine to select one or more analog input channels. the channel selection should be changed only when the adst bit is cleared to ?. group select channel select selected channels ch2 ch1 ch0 single mode scan mode 0 0 0 an 0 (initial value) an 0 0 1 an 1 an 0 , an 1 1 0 an 2 an 0 to an 2 1 1 an 3 an 0 to an 3 1 0 0 an 4 an 4 0 1 an 5 an 4 , an 5 1 0 an 6 an 4 to an 6 1 1 an 7 an 4 to an 7 214 9.2.3 a/d control register (adcr)?'ffea bit 7 6 5 4 3 2 1 0 trge chs initial value 0 1 1 1 1 1 1 0 read/write r/w r/w the a/d control register (adcr) is an 8-bit readable/writable register that enables or disables the a/d external trigger signal. the adcr is initialized to h'7e at a reset and in the standby modes. bit 7?rigger enable (trge): this bit enables the adtrg (a/d external trigger) signal to set the adst bit and start a/d conversion. bit 7 trge description 0 a/d external trigger is disabled. adtrg does not set (initial value) the adst bit. 1 a/d external trigger is enabled. adtrg sets the adst bit. (the adst bit can also be set by software.) bits 6 to 1?eserved: these bits cannot be modified and are always read as ?. bit 0?hannel set select (chs): this bit is reserved. it does not affect the operation of the chip. 215 9.3 operation the a/d converter performs 8 successive approximations to obtain a result ranging from h'00 (corresponding to av ss ) to h'ff (corresponding to av cc ). the a/d converter module can be programmed to operate in single mode or scan mode as explained below. 9.3.1 single mode (scan = 0) the single mode is suitable for obtaining a single data value from a single channel. a/d conversion starts when the adst bit is set to ?,?either by software or by a high-to-low transition of the adtrg signal (if enabled). during the conversion process the adst bit remains set to ?.? when conversion is completed, the adst bit is automatically cleared to ?. when the conversion is completed, the adf bit is set to ?.? if the interrupt enable bit (adie) is also set to ?,?an a/d conversion end interrupt (adi) is requested, so that the converted data can be processed by an interrupt-handling routine. the adf bit is cleared when software reads the a/d control/status register (adcsr), then writes a ??in this bit. before selecting the single mode, clock, and analog input channel, software should clear the adst bit to ??to make sure the a/d converter is stopped. changing the mode, clock, or channel selection while a/d conversion is in progress can lead to conversion errors. a/d conversion begins when the adst bit is set to ??again. the same instruction can be used to alter the mode and channel selection and set adst to ?. 216 the following example explains the a/d conversion process in single mode when channel 1 (an1) is selected and the external trigger is disabled. figure 9-2 shows the corresponding timing chart. (1) software clears the adst bit to ?,?then selects the single mode (scan = ?? and channel 1 (ch2 to ch0 = ?01?, enables the a/d interrupt request (adie = ??, and sets the adst bit to ??to start a/d conversion. coding example: (when using the slow clock, cks = ?? bclr #5, @h'ffe8 ;clear adst mov.b #h'7f, rol mov.b rol, @h'ffea ;disable external trigger mov.b #h'61, rol mov.b rol, @h'ffe8 ;select mode and channel and set adst to ? value set in adcsr: adf adie adst scan cks ch2 ch1 ch0 0 1 1 0 0 0 0 1 (2) the a/d converter converts the voltage level at the an 1 input pin to a digital value. at the end of the conversion process the a/d converter transfers the result to register addrb, sets the adf bit to ?,?clears the adst bit to ?,? and halts. (3) adf = ??and adie = ?,?so an a/d interrupt is requested. (4) the user-coded a/d interrupt-handling routine is started. (5) the interrupt-handling routine reads the adcsr value, then writes a ??in the adf bit to clear this bit to ?. (6) the interrupt-handling routine reads addrb and processes the a/d conversion result. (7) the routine ends. steps (2) to (7) can now be repeated by setting the adst bit to ??again. 217 note: * indicates execution of a software instruction waiting a/d conver- sion waiting a/d conver- sion waiting waiting waiting waiting set * y clear * y a/d conversion starts y set * y y read result read result a/d conversion result a/d conversion result set * y clear * y y adst adf channel 0 (an 0 ) channel 1 (an 1 ) channel 2 (an 2 ) channel 3 (an 3 ) addra addrb addrc addrd interrupt (adi) adie figure 9-3 figure 9-2. a/d operation in single mode (when channel 1 is selected) 218 9.3.2 scan mode (scan = 1) the scan mode can be used to monitor analog inputs on one or more channels. when the adst bit is set to ?,?either by software or by a high-to-low transition of the adtrg signal (if enabled), a/d conversion starts from the first channel selected by the ch bits. when ch2 = ??the first channel is an 0 . when ch2 = ??the first channel is an 4 . if the scan group includes more than one channel (i.e., if bit ch1 or ch0 is set), conversion of the next channel (an 1 or an 5 )begins as soon as conversion of the first channel ends. conversion of the selected channels continues cyclically until the adst bit is cleared to ?.? the conversion results are placed in the data registers corresponding to the selected channels. the a/d data registers are readable by the cpu. before selecting the scan mode, clock, and analog input channels, software should clear the adst bit to ??to make sure the a/d converter is stopped. changing the mode, clock, or channel selection while a/d conversion is in progress can lead to conversion errors. a/d conversion begins from the first selected channel when the adst bit is set to ??again. the same instruction can be used to alter the mode and channel selection and set adst to ?. the following example explains the a/d conversion process when three channels in group 0 are selected (an 0 , an 1 , and an 2 ) and the external trigger is disabled. figure 9-3 shows the corresponding timing chart. (1) software clears the adst bit to ?,?then selects the scan mode (scan = ??, scan group 0 (ch2 = ??, and analog input channels an 0 to an 2 (ch1 = ?? ch0 = ?? and sets the adst bit to ??to start a/d conversion. coding example: (with slow clock and adi interrupt enabled) bclr #5, @h'ffe8 ;clear adst mov.b #h'7f, rol mov.b rol, @h'ffea ;disable external trigger mov.b #h'72, rol mov.b rol, @h'ffe8 ;select mode and channels and set adst to ? value set in adcsr adf adie adst scan cks ch2 ch1 ch0 0 1 1 1 0 0 1 0 219 (2) the a/d converter converts the voltage level at the an 0 input pin to a digital value, and transfers the result to register addra. (3) next the a/d converter converts an 1 and transfers the result to addrb. then it converts an 2 and transfers the result to addrc. (4) after all selected channels (an 0 to an 2 ) have been converted, the ad converter sets the adf bit to ?.? if the adie bit is set to ?,?an a/d interrupt (adi) is requested. then the a/d converter begins converting an 0 again. (5) steps (2) to (4) are repeated cyclically as long as the adst bit remains set to ?. to stop the a/d converter, software must clear the adst bit to ?. regardless of which channel is being converted when the adst bit is cleared to ?,?when the adst bit is set to ??again, conversion begins from the the first selected channel (an 0 ). 220 adst adf channel 0 (an 0 ) channel 1 (an 1 ) channel 2 (an 2 ) channel 3 (an 3 ) addra addrb addrc addrd continuous a/d conversion set clear clear a/d conversion time waiting a/d conver- sion waiting a/d conver- sion ? waiting waiting a/d conver- sion waiting a/d conver- sion waiting waiting a/d conver- sion a waiting waiting transfer a/d conver- sion result a/d conversion result ? a/d conversion result a/d conversion result a y y y ? * 1 indicates execution of a software instruction data undergoing conversion when adst bit is cleared are ignored. y notes: figure 9-4 * 1 * 1 * 2 * 1 * 2 figure 9-3. a/d operation in scan mode (when channels 0 to 2 are selected) 221 9.3.3 input sampling time and a/d conversion time the a/d converter includes a built-in sample-and-hold circuit. sampling of the input starts at a time t d after the adst bit is set to ?.? the sampling process lasts for a time t spl . the actual a/d conversion begins after sampling is completed. figure 9-4 shows the timing of these steps. table 9-4 (a) lists the conversion times for the single mode. table 9-4 (b) lists the conversion times for the scan mode. the total conversion time (t conv ) includes t d and t spl . the purpose of t d is to synchronize the adcsr write time with the a/d conversion process, so the length of t d is variable. the total conversion time therefore varies within the minimum to maximum ranges indicated in table 9-4 (a) and (b). in the scan mode, the ranges given in table 9-4 (b) apply to the first conversion. the length of the second and subsequent conversion processes is fixed at 256 states (when cks = ?? or 128 states (when cks = ??. figure 9-4. a/d conversion timing internal address bus write signal input sampling timing adf t d t spl (1) (2) t conv figure 9-4 (1): adcsr write cycle (2): adcsr address t d : synchronization delay t spl : input sampling time t conv : total a/d conversion time 222 table 9-4 (a). a/d conversion time (single mode) cks = ? cks = ? item symbol min typ max min typ max synchronization delay t d 18 33 10 17 input sampling time t spl 63 31 total a/d conversion time t conv 227 242 115 122 table 9-4 (b). a/d conversion time (scan mode) cks = ? cks = ? item symbol min typ max min typ max synchronization delay t d 18 33 10 17 input sampling time t spl 63 31 total a/d conversion time t conv 259 274 131 138 note: values in the tables above are numbers of states. 9.3.4 external trigger input timing a/d conversion can be started by external trigger input at the adtrg pin. this input is enabled or disabled by the trge bit in the a/d control register (adcr). if the trge bit is set to ?,?when a falling edge of adtrg is detected the adst bit is set to ??and a/d conversion begins. subsequent operation in both single and scan modes is the same as when the adst bit is set to ? by software. figure 9-5 shows the trigger timing. 223 figure 9-5. external trigger input timing 9.4 interrupts the a/d conversion module generates an a/d-end interrupt request (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in the a/d control/status register (adcsr). adtrg internal trigger signal adst a/d conversion fig. 9-5 224 section 10. ram 10.1 overview the h8/329 and h8/328 include 1k byte of on-chip static ram. the h8/327 has 512 bytes. the h8/326 has 256 bytes. the on-chip ram is connected to the cpu by a 16-bit data bus. both byte and word access to the on-chip ram are performed in two states, enabling rapid data transfer and instruction execution. the on-chip ram is assigned to addresses h'fb80 to h'ff7f in the h8/329 and h8/328, addresses h'fd80 to h'ff7f in the h8/327, and addresses h'fe80 to h'ff7f in the h8/326. the rame bit in the system control register (syscr) can enable or disable the on-chip ram, permitting these addresses to be allocated to external memory instead, if so desired. 10.2 block diagram figure 10-1 is a block diagram of the on-chip ram. figure 10-1. block diagram of on-chip ram (h8/329 and h8/328) h'ff7e internal data bus (lower 8 bits) internal data bus (upper 8 bits) h'ff7f h'fb82 h'fb80 h'fb83 h'fb81 even address odd address on-chip ram fig. 10-1 225 10.3 ram enable bit (rame) in system control register (syscr) the on-chip ram is enabled or disabled by the rame (ram enable) bit in the system control register (syscr). bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg rame initial value 0 0 0 0 1 0 1 1 read/write r/w r/w r/w r/w r/w r/w the only bit in the system control register that concerns the on-chip ram is the rame bit. see section 2.2, ?ystem control register?for the other bits. bit 0?am enable (rame): this bit enables or disables the on-chip ram. the rame bit is initialized to ??on the rising edge of the res signal, so a reset enables the on- chip ram. the rame bit is not initialized in the software standby mode. bit 7 rame description 0 on-chip ram is disabled. 1 on-chip ram is enabled. (initial value) 10.4 operation 10.4.1 expanded modes (modes 1 and 2) if the rame bit is set to ?,?accesses to addresses h'fb80 to h'ff7f in the h8/329 and h8/328, addresses h'fd80 to h'ff7f in the h8/327, and addresses h'fe80 to h'ff7f in the h8/326 are directed to the on-chip ram. if the rame bit is cleared to ?,?accesses to these addresses are directed to the external data bus. 10.4.2 single-chip mode (mode 3) if the rame bit is set to ?,?accesses to addresses h'fb80 to h'ff7f in the h8/329 and h8/328, addresses h'fd80 to h'ff7f in the h8/327, and addresses h'fe80 to h'ff7f in the h8/326 are directed to the on-chip ram. if the rame bit is cleared to ?,?the on-chip ram data cannot be accessed. attempted write access has no effect. attempted read access always results in h'ff data being read. 226 section 11. rom 11.1 overview the h8/329 includes 32k bytes of high-speed, on-chip rom. the h8/328 has 24k bytes. the h8/327 has 16k bytes. the h8/326 has 8k bytes. the on-chip rom is connected to the cpu via a 16-bit data bus. both byte data and word data are accessed in two states, enabling rapid data transfer and instruction fetching. the h8/329 and h8/327 are available with electrically programmable rom (prom). the prom version has a prom mode in which the chip can be programmed with a standard prom writer. the on-chip rom is enabled or disabled depending on the mcu operating mode, which is determined by the inputs at the mode pins (md 1 and md 0 ). see table 11-1. table 11-1. on-chip rom usage in each mcu mode mode pins mode md 1 md 0 on-chip rom mode 1 (expanded mode) 0 1 disabled (external addresses) mode 2 (expanded mode) 1 0 enabled mode 3 (single-chip mode) 1 1 enabled 227 11.1.1 block diagram figure 11-1 is a block diagram of the on-chip rom. figure 11-1. block diagram of on-chip rom (h8/329) 11.2 prom mode (h8/329, h8/327) 11.2.1 prom mode setup in the prom mode of the prom version of the h8/329 and h8/327, the usual microcomputer functions are halted to allow the on-chip prom to be programmed. the programming method is the same as for the hn27c256. to select the prom mode, apply the signal inputs listed in table 11-2. table 11-2. selection of prom mode pin input mode pin md 1 low mode pin md 0 low stby pin low pins p6 3 and p6 4 high h'0002 h'0000 internal data bus (lower 8 bits) internal data bus (upper 8 bits) h'0003 h'0001 h'7fff h'7ffe on-chip rom even addresses odd addresses fig. 11-1 228 11.2.2 socket adapter pin assignments and memory map the h8/329 and h8/327 can be programmed with a general-purpose prom writer. since the package has more than 32 pins, a socket adapter is necessary. table 11-3 lists recommended socket adapters. figure 11-2 shows the socket adapter pin assignments by giving the correspondence between h8/329 or h8/327 pins and hn27c256 pin functions. the same socket adapter can be used for both the h8/329 and h8/327. figures 11-3 and 11-4 show memory maps in the prom mode. since the h8/329 has only 32k bytes of on-chip prom, its address range should be specified as h'0000 to h'7fff. since the h8/327 has only 16k bytes of on-chip prom, its address range should be specified as h'0000 to h'3fff. h'ff data should be specified for unused address areas. it is important to limit the program address range to h'0000 to h'7fff for the h8/329, and to h'0000 to h'3fff for the h8/327, and specify h'ff data for h'8000 or h'4000 and higher addresses. if data (other than h'ff) are written by mistake in addresses equal to or greater than h'8000 in the h8/329, or h'4000 in the h8/327, it may become impossible to program or verify the prom data. with a windowed package, it is possible to erase the data and reprogram, but this cannot be done with a plastic package, so particular care is required. table 11-3. recommended socket adapters package recommended socket adapter 64-pin windowed shrink dip (dc-64s) hs328ess02h 64-pin shrink dip (dp-64s) 64-pin qfp (fp-64a) hs328esh02h 68-pin plcc (dp-68) hs328esc02h 229 figure 11-2. socket adapter pin assignments cp-68 13 14 61 62 63 64 65 66 67 68 60 59 58 57 56 55 54 53 50 49 48 47 46 45 44 43 37 38 32 15 42 22 21 16 23 17 51 1 18 35 52 dc-64s dp-64s pin res nmi p3 p3 p3 p3 p3 p3 p3 p3 p1 p1 p1 p1 p1 p1 p1 p1 p2 p2 p2 p2 p2 p2 p2 p2 p6 p6 av v v md md stby av v v v v v v 12 13 57 58 59 60 61 62 63 64 56 55 54 53 52 51 50 49 47 46 45 44 43 42 41 40 34 35 30 14 39 20 19 15 21 16 48 ? ? ? ? pin v ea eo eo eo eo eo eo eo eo ea ea ea ea ea ea ea ea ea oe ea ea ea ea ea ce v v hn27c256 (28 pins) 1 24 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 22 21 23 2 26 27 20 28 14 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 3 4 cc cc cc 0 1 ss ss ss ss ss ss ss 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 10 11 12 13 14 pp cc h8/329 or h8/327 eprom socket note: all pins not listed in this figure should be left open. v : eo to eo : ea to ea : oe: ce: pp 0 7 0 14 program voltage (12.5 v) data input/output address input output enable chip enable h8/329 u.m. '92 fig. 11-2 ss fp-64a 4 5 49 50 51 52 53 54 55 56 48 47 46 45 44 43 42 41 39 38 37 36 35 34 33 32 26 27 22 8 31 12 11 7 13 8 40 ? ? ? ? 230 figure 11-3. memory map of h8/329 in prom mode figure 11-4. memory map of h8/327 in prom mode h'7fff h'7fff address in prom mode address in mcu mode on-chip prom fig. 11-3 h'0000 h'0000 h'3fff h'3fff ??output * * if this area is read in prom mode, the output data are h'ff. h'7fff address in prom mode address in mcu mode h'0000 h'0000 on-chip prom note: fig. 11-4 231 11.3 programming the write, verify, and other sub-modes of the prom mode are selected as shown in table 11-4. table 11-4. selection of sub-modes in prom mode sub-mode ce oe v pp v cc eo 7 to eo 0 ea 14 to ea 0 write low high v pp v cc data input address input verify high low v pp v cc data output address input programming high high v pp v cc high impedance address input inhibited note: the v pp and v cc pins must be held at the v pp and v cc voltage levels. the h8/329 and h8/327 prom has the same standard read/write specifications as the hn27c256 and hn27256 eprom. 11.3.1 writing and verifying an efficient, high-speed programming procedure can be used to write and verify prom data. this procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. it leaves the data h'ff written in unused addresses. figure 11-5 shows the basic high-speed programming flowchart. tables 11-5 and 11-6 list the electrical characteristics of the chip in the prom mode. figure 11-6 shows a write/verify timing chart. 232 figure 11-5. high-speed programming flowchart start address = 0 n = 0 set read mode v cc = 5.0v 0.5v, v pp = v cc end yes no yes no yes n < 25? all addresses read? error no yes n + 1 ? n address + 1 ? address no last address? write time t pw = 1 ms 5% write t opw = 3n ms verify ok? set program/verify mode v cc = 6.0v 0.25v, v pp = 12.5v 0.3v fig. 11-5 233 table 11-5. dc characteristics (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, v ss = 0v, ta = 25?c 5?c) measurement item symbol min typ max unit conditions input high voltage eo 7 e eo 0 , v ih 2.4 ? v cc + 0.3 v ea 14 e ea 0 , oe, ce input low voltage eo 7 e eo 0 , v il e0.3 ? 0.8 v ea 14 e ea 0 , oe, ce output high voltage eo 7 e eo 0 v oh 2.4 ? ? v i oh = e200a output low voltage eo 7 e eo 0 v ol ? ? 0.45 v i ol = 1.6ma input leakage eo 7 e eo 0 , |i li | ? ? 2 a v in = 5.25v/ current ea 14 e ea 0 , 0.5v oe, ce v cc current i cc ? ? 40 ma v pp current i pp ? ? 40 ma table 11-6. ac characteristics (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, ta = 25?c 5?c) measurement item symbol min typ max unit conditions address setup time t as 2 ? ? s see figure 11-6* oe setup time t oes 2 ? ? s data setup time t ds 2 ? ? s address hold time t ah 0 ? ? s data hold time t dh 2 ? ? s data output disable time t df ? ? 130 ns vpp setup time t vps 2 ? ? s program pulse width t pw 0.95 1.0 1.05 ms note: * input pulse level: 0.8v to 2.2v input rise/fall time 2 20ns timing reference levels: input?1.0v, 2.0v; output?0.8v, 2.0v 234 table 11-6. ac characteristics (cont.) (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, ta = 25?c 5?c) measurement item symbol min typ max unit conditions oe pulse width for t opw 2.85 ? 78.75 ms see figure 11-6* overwrite-programming v cc setup time t vcs 2 ? ? s data output delay time t oe 0 ? 500 ns note: * input pulse level: 0.8v to 2.2v input rise/fall time 2 20ns timing reference levels: input?1.0v, 2.0v; output?0.8v, 2.0v figure 11-6. prom write/verify timing oe write verify address data input data output data t vps t ds t dh t as t ah t df v pp v pp v cc t vcs t pw t opw t oes t oe v cc fig. 11-6 ce gnd 235 11.3.2 notes on writing (1) write with the specified voltages and timing. the programming voltage (v pp ) is 12.5v. caution: applied voltages in excess of the specified values can permanently destroy the chip. be particularly careful about the prom writer?s overshoot characteristics. if the prom writer is set to hitachi hn27256 or hn27c256 specifications, or to intel specifications, v pp will be 12.5v. (2) before writing data, check that the socket adapter and chip are correctly mounted in the prom writer. overcurrent damage to the chip can result if the index marks on the prom writer, socket adapter, and chip are not correctly aligned. (3) don?t touch the socket adapter or chip while writing. touching either of these can cause contact faults and write errors. 11.3.3 reliability of written data an effective way to assure the data holding characteristics of the programmed chips is to bake them at 150?c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 11-7 shows the recommended screening procedure. 236 figure 11-7. recommended screening procedure if a series of write errors occurs while the same prom writer is in use, stop programming and check the prom writer and socket adapter for defects, using a microcomputer chip with a windowed package and on-chip eprom. please inform hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. 11.3.4 erasing of data the windowed package enables data to be erased by illuminating the window with ultraviolet light. table 11-7 lists the erasing conditions. table 11-7. erasing conditions item value ultraviolet wavelength 253.7 nm minimum illumination 15ws/cm 2 the conditions in table 11-7 can be satisfied by placing a 12000w/cm 2 ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes. write and verify program read and check program v cc = 4.5v and 5.5v install note: * baking time should be measured from the point when the baking oven reaches 150 c. bake with power off 150 10 c, 48 hr + 8 hr * ?0 hr fig. 11-7 237 11.4 handling of windowed packages (1) glass erasing window: rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. if the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light. this returns the chip to its normal condition, but it also reduces the charge stored in the floating gates of the prom, so it is recommended that the chip be reprogrammed afterward. accumulation of static charge on the window surface can be prevented by the following precautions: ? when handling the package, ground yourself. don?t wear gloves. avoid other possible sources of static charge. - avoid friction between the glass window and plastic or other materials that tend to accumulate static charge. ? be careful when using cooling sprays, since they may have a slight ion content. cover the window with an ultraviolet-shield label, preferably a label including a conductive material. besides protecting the prom contents from ultraviolet light, the label protects the chip by distributing static charge uniformly. (2) handling after programming: fluorescent light and sunlight contain small amounts of ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. in addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. it is recommended that after programming the chip, you cover the erasing window with a light-proof label (such as an ultraviolet-shield label). 238 section 12. power-down state 12.1 overview the h8/329 series has a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. the power-down state includes three modes: (1) sleep mode ?a software-triggered mode in which the cpu halts but the rest of the chip remains active (2) software standby mode ?a software-triggered mode in which the entire chip is inactive (3) hardware standby mode ?a hardware-triggered mode in which the entire chip is inactive table 12-1 lists the conditions for entering and leaving the power-down modes. it also indicates the status of the cpu, on-chip supporting modules, etc. in each power-down mode. table 12-1. power-down state entering cpu sup. i/o exiting mode procedure clock cpu reg s. mod. ram ports methods sleep execute run halt held run held held interrupt mode sleep res instruction stby soft- set ssby bit halt halt held halt held held nmi ware in syscr to and irq 0 ?irq 2 standby ?,?then initial- stby mode execute sleep ized res instruction hard- set stby halt halt not halt held high stby high, ware pin to low held and impe- then res standby level initialized dance low ? high mode state notes: 1. syscr: system control register 2. ssby: software standby bit 239 12.2 system control register: power-down control bits bits 7 to 4 of the system control register (syscr) concern the power-down state. specifically, they concern the software standby mode. table 12-2 lists the attributes of the system control register. table 12-2. system control register name abbreviation r/w initial value address system control register syscr r/w h'0b h'ffc4 bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg rame initial value 0 0 0 0 1 0 1 1 read/write r/w r/w r/w r/w r/w r/w bit 7?oftware standby (ssby): this bit enables or disables the transition to the software standby mode. on recovery from the software standby mode by an external interrupt, ssby remains set to ?. to clear this bit, software must write a ?. bit 7 ssby description 0 the sleep instruction causes a transition to the sleep mode. (initial value) 1 the sleep instruction causes a transition to the software standby mode. bits 6 to 4?tandby timer select 2 to 0 (sts2 to sts0): these bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. during the selected time, the clock oscillator runs but clock pulses are not supplied to the cpu or the on-chip supporting modules. 240 bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 settling time = 8192 states (initial value) 0 0 1 settling time = 16384 states 0 1 0 settling time = 32768 states 0 1 1 settling time = 65536 states 1 settling time = 131072 states when the on-chip clock generator is used, the sts bits should be set to allow a settling time of at least 10ms. table 12-3 lists the settling times selected by these bits at several clock frequencies and indicates the recommended settings. when the chip is externally clocked, the sts bits can be set to any value. the minimum value (sts2 = sts1 = sts0 = ?? is recommended. table 12-3. times set by standby timer select bits (unit: ms) settling time system clock frequency (mhz) sts2 sts1 sts0 (states) 10 8 6 4 2 1 0.5 0 0 0 8192 0.8 1.0 1.3 2.0 4.1 8.2 16.4 0 0 1 16384 1.6 2.0 2.7 4.1 8.2 16.4 32.8 0 1 0 32768 3.3 4.1 5.5 8.2 16.4 32.8 65.5 0 1 1 65536 6.6 8.2 10.9 16.4 32.8 65.5 131.1 1 131072 13.1 16.4 21.8 32.8 65.5 131.1 262.1 notes: 1. all times are in milliseconds. 2. recommended values are printed in boldface. 241 12.3 sleep mode the sleep mode provides an effective way to conserve power while the cpu is waiting for an external interrupt or an interrupt from an on-chip supporting module. 12.3.1 transition to sleep mode when the ssby bit in the system control register is cleared to ?,?execution of the sleep instruction causes a transition from the program execution state to the sleep mode. after executing the sleep instruction, the cpu halts, but the contents of its internal registers remain unchanged. the on-chip supporting modules continue to operate normally. 12.3.2 exit from sleep mode the chip wakes up from the sleep mode when it receives an internal or external interrupt request, or a low input at the res or stby pin. (1) wake-up by interrupt: an interrupt releases the sleep mode and starts the cpu s interrupt- handling sequence. if an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module s control register, the interrupt cannot be requested, so it cannot wake the chip up. similarly, the cpu cannot be awoken by an interrupt other than nmi if the i (interrupt mask) bit in the ccr (condition code register) is set when the sleep instruction is executed. (2) wake-up by res pin: when the res pin goes low, the chip exits from the sleep mode to the reset state. (3) wake-up by stby pin: when the stby pin goes low, the chip exits from the sleep mode to the hardware standby mode. 242 12.4 software standby mode in the software standby mode, the system clock stops and chip functions halt, including both cpu functions and the functions of the on-chip supporting modules. power consumption is reduced to an extremely low level. the on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained (at least 2v), the contents of the cpu registers and on-chip ram remain unchanged. 12.4.1 transition to software standby mode to enter the software standby mode, set the standby bit (ssby) in the system control register (syscr) to ?,?then execute the sleep instruction. 12.4.2 exit from software standby mode the chip can be brought out of the software standby mode by an input at one of six pins: nmi, irq 0 , irq 1 , irq 2 , res, or stby. (1) recovery by external interrupt: when an nmi, irq 0 , irq 1 , or irq 2 request signal is received, the clock oscillator begins operating. after the waiting time set in the system control register (bits sts2 to sts0), clock pulses are supplied to the cpu and on-chip supporting modules. the cpu executes the interrupt-handling sequence for the requested interrupt, then returns to the instruction after the sleep instruction. the ssby bit is not cleared. see section 12.2, ?ystem control register: power-down control bits,?for information about the sts bits. (2) recovery by res pin: when the res pin goes low, the clock oscillator starts and clock pulses are supplied to the entire chip. next, when the res pin goes high, the cpu begins executing the reset sequence. the ssby bit is cleared to ?. the res pin must be held low long enough for the clock to stabilize. (3) recovery by stby pin: when the stby pin goes low, the chip exits from the software standby mode to the hardware standby mode. 243 12.4.3 sample application of software standby mode in this example the chip enters the software standby mode when nmi goes low and exits when nmi goes high, as shown in figure 12-1. the nmi edge bit (nmieg) in the system control register is originally cleared to ?,?selecting the falling edge. when nmi goes low, the nmi interrupt handling routine sets nmieg to ?,?sets ssby to ??(selecting the rising edge), then executes the sleep instruction. the chip enters the software standby mode. it recovers from the software standby mode on the next rising edge of nmi. figure 12-1. software standby mode (when) nmi timing 12.4.4 application note the i/o ports retain their current states in the software standby mode. if a port is in the high output state, the current dissipation caused by the high output current is not reduced. clock generator nmi ssby nmieg settling time nmi interrupt handler nmieg = ? ssby = ? software standby mode (power-down state) nmi interrupt handler sleep figure 12-1 244 12.5 hardware standby mode 12.5.1 transition to hardware standby mode regardless of its current state, the chip enters the hardware standby mode whenever the stby pin goes low. the hardware standby mode reduces power consumption drastically by halting the cpu, stopping all the functions of the on-chip supporting modules, and placing i/o ports in the high-impedance state. the registers of the on-chip supporting modules are reset to their initial values. only the on- chip ram is held unchanged, provided the minimum necessary voltage supply is maintained (at least 2v). notes: 1. the rame bit in the system control register should be cleared to ??before the stby pin goes low, to disable the on-chip ram during the hardware standby mode. 2. do not change the inputs at the mode pins (md1, md0) during hardware standby mode. be particularly careful not to let both mode pins go low in hardware standby mode, since that places the chip in prom mode and increases current dissipation. 12.5.2 recovery from hardware standby mode recovery from the hardware standby mode requires inputs at both the stby and res pins. when the stby pin goes high, the clock oscillator begins running. the res pin should be low at this time and should be held low long enough for the clock to stabilize. when the res pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state. 245 12.5.3 timing relationships figure 12-2 shows the timing relationships in the hardware standby mode. in the sequence shown, first res goes low, then stby goes low, at which point the chip enters the hardware standby mode. to recover, first stby goes high, then after the clock settling time, res goes high. figure 12-2. hardware standby mode timing clock pulse generator res stby clock settling time restart figure 12-2 246 section 13. clock pulse generator 13.1 overview the h8/329 series has a built-in clock pulse generator (cpg) consisting of an oscillator circuit, a system () clock divider, and a prescaler. the prescaler generates clock signals for the on-chip supporting modules. 13.1.1 block diagram figure 13-1. block diagram of clock pulse generator 13.2 oscillator circuit if an external crystal is connected across the extal and xtal pins, the on-chip oscillator circuit generates a clock signal for the system clock divider. alternatively, an external clock signal can be applied to the extal pin. (1) connecting an external crystal ? circuit configuration: an external crystal can be connected as in the example in figure 13-2. an at-cut parallel resonating crystal should be used. cpg oscillator circuit divider ?2 prescaler /2 to /4096 xtal extal 247 figure 13-2. connection of crystal oscillator (example) - crystal oscillator: figure 15-3 shows an equivalent circuit of the external crystal. the external crystal should have the characteristics listed in table 13-1. table 13-1. external crystal parameters frequency (mhz) 2 4 8 12 16 20 rs max ( ) 500 120 60 40 30 20 c 0 (pf) 7 pf max figure 13-3. equivalent circuit of external crystal ? note on board design: when an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. see figure 13-4. the crystal and its load capacitors should be placed as close as possible to the xtal and extal pins. extal xtal c l1 c l1 = c l2 = 10 to 22pf c l2 c l c 0 xtal extal l r s at-cut parallel resonating crystal figure 13-3 248 figure 13-4. notes on board design around external crystal (2) input of external clock signal ? circuit configuration: an external clock signal can be input as shown in the examples in figure 13-5. in example (b), the external clock should be held high during standby. figure 13-5. external clock input (example) figure 13-5 extal xtal external clock input 74hc04 (b) extal xtal external clock input open (a) not allowed signal a signal b h8/327 xtal extal c l1 c l2 figure 13-4 249 - external clock input frequency double the system clock () frequency duty factor 45% to 55% 13.3 system clock divider the system clock divider divides the crystal oscillator or external clock frequency by 2 to create the system clock (). 250 section 14. electrical specifications 14.1 absolute maximum ratings table 14-1 lists the absolute maximum ratings. table 14-1. absolute maximum ratings item symbol rating unit supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +13.5 v input voltage ports 1 ?6 v in ?.3 to v cc + 0.3 v port 7 v in ?.3 to av cc + 0.3 v analog supply voltage av cc ?.3 to +7.0 v analog input voltage v an ?.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?0 to +75 ?c wide-range specifications: ?40 to +85 ?c storage temperature t stg ?5 to +125 ?c note: exceeding the absolute maximum ratings shown in table 14-1 can permanently destroy the chip. 14.2 electrical characteristics 14.2.1 dc characteristics table 14-2 lists the dc characteristics of the 5v versions of the h8/329 series. table 14-3 lists the dc characteristics of the 3v versions. table 14-4 gives the allowable current output values of the 5v versions. table 14-5 gives the allowable current output values of the 3v versions. 251 table 14-2. dc characteristics (5v versions) conditions: v cc = 5.0v 10%, av cc = 5.0v 10%*, v ss = av ss = 0v, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) measurement item symbol min typ max unit conditions schmitt trigger p6 7 ?p6 2 , p6 0 , v t - 1.0 v input voltage p4 7 , p4 4 ?p4 0 v t + v cc 0.7 v (1) v t + ? t - 0.4 v input high voltage res, stby , nmi v ih v cc ?0.7 v cc + 0.3 v (2) md 1 , md 0 extal p7 7 ?p7 0 2.0 av cc + 0.3 v input high voltage input pins v ih 2.0 v cc + 0.3 v other than (1) and (2) above input low voltage res, stby v il ?.3 0.5 v (3) md 1 , md 0 input low voltage input pins v il ?.3 0.8 v other than (1) and (3) above output high all output pins v oh v cc ?0.5 v i oh = ?00 a voltage 3.5 v i oh = ?.0ma output low all output pins v ol 0.4 v i ol = 1.6ma voltage ports 1 and 2 1.0 v i ol = 10.0ma input leakage res |i in | 10.0 a v in = 0.5v to current stby, nmi, 1.0 a v cc ?0.5v md 1 , md 0 p7 7 ?p7 0 1.0 a v in = 0.5v to av cc ?0.5v leakage current ports 1, 2, 3 |i tsi | 1.0 a v in = 0.5v to in 3-state (off state) 4, 5, 6 v cc ?0.5v input pull-up ports 1, 2, 3 ?p 30 250 a v in = 0v mos current note: * connect av cc to the power supply (v cc ) even when the a/d converter is not used. 252 table 14-2. dc characteristics (5v versions) (cont.) conditions: v cc = 5.0v 10%, av cc = 5.0v 10% *1 , v ss = av ss = 0v, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) measurement item symbol min typ max unit conditions input capacitance res c in 60 pf v in = 0v nmi 30 pf f = 1mhz all input pins 15 pf ta = 25?c except res and nmi current normal i cc 12 25 ma f = 6mhz dissipation *2 operation 16 30 ma f = 8mhz 20 40 ma f = 10mhz sleep mode 8 15 ma f = 6mhz 10 20 ma f = 8mhz 12 25 ma f = 10mhz standby modes *3 0.01 5.0 a analog supply during a/d ai cc 0.6 1.5 ma current conversion waiting 0.01 5.0 a ram standby v ram 2.0 v voltage notes: *1 connect av cc to the power supply (+5v) even when the a/d converter is not used. *2 current dissipation values assume that v ih min = v cc ?0.5v, v il max = 0.5v, all output pins are in the no-load state, and all input pull-up transistors are off. *3 for these values it is assumed that v ram v cc < 4.5v and v ih min = v cc 0.9, v il max = 0.3v. 253 table 14-3. dc characteristics (3v versions) conditions: v cc = 3.0v 10%, av cc = 5.0v 10% *1 , v ss = av ss = 0v, ta = ?0 to 75?c measurement item symbol min typ max unit conditions schmitt p6 7 ?p6 2 , p6 0 , v t v cc 0.15 v trigger input p4 7 , p4 4 ?p4 0 v t + v cc 0.7 v voltage *2 v t + ? t 0.2 v (1) input high res, stby v ih v cc 0.9 v cc + 0.3 v voltage *2 md 1, md 0 (2) extal, nmi p7 7 ?p7 0 v cc 0.7 av cc + 0.3 v input pins v cc 0.7 v cc + 0.3 v other than (1) and (2) above input low res, stby v il ?.3 v cc 0.1 v voltage *2 md 1, md 0 (3) input pins ?.3 v cc 0.15 v other than (1) and (3) above output high all output pins v oh v cc ?0.4 v i oh = ?00 a voltage v cc ?0.9 v i oh = ?ma output low all output pins v ol 0.4 v i ol = 0.8ma voltage ports 1 and 2 0.4 v i ol = 1.6ma input res |i in | 10.0 a v in = 0.5 to leakage stby, nmi, 1.0 a v cc ?0.5v current md 1 , md 0 p7 7 ?p7 0 1.0 a v in = 0.5 to av cc ?0.5v leakage ports 1, 2, 3 |i tsi | 1.0 a v in = 0.5 to current in 4, 5, 6 v cc ?0.5v 3-state (off state) input ports 1, 2, 3 ? p 3 120 a v in = 0v pull-up mos current notes: *1 connect av cc to the power supply (v cc ) even when the a/d converter is not used. *2 in the range 3.3v < v cc < 4.5v, for the input levels of v ih and v t , apply the higher of the values given for the 5v and 3v versions. for v il and v t , apply the lower of the values given for the 5v and 3v versions. 254 table 14.3. dc characteristics (3v versions) (cont.) conditions: v cc = 3.0v 10%, av cc = 5.0v 10% *1 , v ss = av ss = 0v, ta = ?0 to 70?c measurement item symbol min typ max unit conditions input res c in 60 pf v in = 0v capacitance nmi 30 pf f = 1mhz all input pins 15 pf ta = 25?c except res and nmi current normal i cc 4 ma f = 3mhz dissipation *2 operation 6 12 ma f = 5mhz sleep mode 3 ma f = 3mhz 4 8 ma f = 5mhz standby modes *3 0.01 5.0 a analog during a/d ai cc 0.6 1.5 ma supply conversion current waiting 0.01 5.0 a ram backup voltage v ram 2.0 v (in standby modes) notes: *1 connect av cc to the power supply (+3v) even when the a/d converter is not used. *2 current dissipation values assume that v ih min. = v cc ?0.5v, v il max. = 0.5v, all output pins are in the no-load state, and all input pull-up transistors are off. *3 for these values it is assumed that v ram v cc < 2.7v and v ih min = v cc 0.9, v il max = 0.3v. 255 table 14-4. allowable output current values (5v versions) conditions: v cc = 5.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) item symbol min typ max unit allowable output low ports 1 and 2 i ol 10 ma current (per pin) other output pins 2.0 ma allowable output low ports 1 and 2, total s i ol 80 ma current (total) total of all output 120 ma allowable output high all output pins ? oh 2.0 ma current (per pin) allowable output high total of all output s ? oh 40 ma current (total) pins table 14-5. allowable output current values (3v versions) conditions: v cc = 3.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, ta = ?0 to 75?c item symbol min typ max unit allowable output low ports 1 and 2 i ol 2 ma current (per pin) other output pins 1 ma allowable output low ports 1 and 2, total s i ol 40 ma current (total) all output pins 60 ma allowable output high all output pins ? oh 2 ma current (per pin) allowable output high total of all output s ? oh 30 ma current (total) pins note: to avoid degrading the reliability of the chip, be careful not to exceed the output current values in tables 14-4 and 14-5. in particular, when driving a darlington transistor pair or led directly, be sure to insert a current-limiting resistor in the output path. see figures 14-1 and 14-2. 256 figure 14-1. example of circuit for driving a darlington pair (5v versions) figure 14-2. example of circuit for driving an led (5v versions) 14.2.2 ac characteristics the ac characteristics of the h8/329 series are listed in three tables. bus timing parameters are given in table 14-6, control signal timing parameters in table 14-7, and timing parameters of the on- chip supporting modules in table 14-8. h8/329 series port 2 k darlington pair fig. 14-1 vcc 600 led port 1 or 2 h8/329 series fig. 14-2 257 table 14-6. bus timing condition a: v cc = 5.0v 10%, v ss = 0v, = 0.5mhz to maximum operating frequency, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) condition b: v cc = 3.0v 10%, v ss = 0v, = 0.5mhz to maximum operating frequency, ta = ?0 to 75?c condition b condition a 5mhz 6mhz 8mhz 10mhz measurement item symbol min max min max min max min max unit conditions clock cycle time t cyc 200 2000 166.7 2000 125 2000 100 2000 ns fig. 14-4 clock pulse width low t cl 70 65 45 35 ns fig. 14-4 clock pulse width high t ch 70 65 45 35 ns fig. 14-4 clock rise time t cr 25 15 15 15 ns fig. 14-4 clock fall time t cf 25 15 15 15 ns fig. 14-4 address delay time t ad 90 70 60 50 ns fig. 14-4 address hold time t ah 30 30 25 20 ns fig. 14-4 address strobe delay time t asd 80 70 60 40 ns fig. 14-4 write strobe delay time t wsd 80 70 60 50 ns fig. 14-4 strobe delay time t sd 90 70 60 50 ns fig. 14-4 write strobe pulse width* t wsw 200 200 150 120 ns fig. 14-4 address setup time 1* t as1 25 25 20 15 ns fig. 14-4 address setup time 2* t as2 105 105 80 65 ns fig. 14-4 read data setup time t rds 90 70 50 35 ns fig. 14-4 read data hold time t rdh 0 0 0 0 ns fig. 14-4 read data access time* t acc 300 270 210 170 ns fig. 14-4 write data delay time t wdd 125 85 75 75 ns fig. 14-4 write data setup time t wds 10 20 10 5 ns fig. 14-4 write data hold time t wdh 30 30 25 20 ns fig. 14-4 wait setup time t wts 60 40 40 40 ns fig. 14-5 wait hold time t wth 20 10 10 10 ns fig. 14-5 note: * values at maximum operating frequency 258 table 14-7. control signal timing condition a: v cc = 5.0v 10%, v ss = 0v, = 0.5mhz to maximum operating frequency, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) condition b: v cc = 3.0v 10%, v ss = 0v, = 0.5mhz to maximum operating frequency, ta = ?0 to 75?c condition b condition a 5mhz 6mhz 8mhz 10mhz measurement item symbol min max min max min max min max unit conditions res setup time t ress 300 200 200 200 ns fig. 14-6 res pulse width t resw 10 10 10 10 tcyc fig. 14-6 nmi setup time t nmis 300 150 150 150 ns fig. 14-7 (nmi, irq 0 to irq 2 ) nmi hold time t nmih 10 10 10 10 ns fig. 14-7 (nmi, irq 0 to irq 2 ) interrupt pulse width t nmiw 300 200 200 200 ns fig. 14-7 for recovery from soft- ware standby mode (nmi, irq 0 to irq 2 ) crystal oscillator settling t osc1 20 20 20 20 ms fig. 14-8 time (reset) crystal oscillator settling t osc2 10 10 10 10 ms fig. 14-9 time (software standby) 259 table 14-8. timing conditions of on-chip supporting modules condition a: v cc = 5.0v 10%, v ss = 0v, = 0.5mhz to maximum operating frequency, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) condition b: v cc = 3.0v 10%, v ss = 0v, = 0.5mhz to maximum operating frequency, ta = ?0 to 75?c condition b condition a 5mhz 6mhz 8mhz 10mhz measurement item symbol min max min max min max min max unit conditions frt timer output delay time t ftod 150 100 100 100 ns fig. 14-10 timer input setup time t ftis 80 50 50 50 ns fig. 14-10 timer clock input t ftcs 80 50 50 50 ns fig. 14-11 setup time timer clock pulse width t ftcwh 1.5 1.5 1.5 1.5 tcyc fig. 14-11 t ftcwl tmr timer output delay time t tmod 150 100 100 100 ns fig. 14-12 timer reset input t tmrs 80 50 50 50 ns fig. 14-14 setup time timer clock input t tmcs 80 50 50 50 ns fig. 14-13 setup time timer clock pulse width t tmcwh 1.5 1.5 1.5 1.5 t cyc fig. 14-13 (single edge) timer clock pulse width t tmcwl 2.5 2.5 2.5 2.5 t cyc fig. 14-13 (both edges) sci input clock (async) t scyc 4 4 4 4 t cyc fig. 14-15 cycle (sync) t scyc 6 6 6 6 t cyc fig. 14-15 transmit data delay t txd 200 100 100 100 ns fig. 14-15 time (sync) receive data setup time t rxs 150 100 100 100 ns fig. 14-15 (sync) receive data hold time t rxh 150 100 100 100 ns fig. 14-15 (sync) input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t scyc fig. 14-16 ports output data delay time t pwd 150 100 100 100 ns fig. 14-17 input data setup time t prs 80 50 50 50 ns fig. 14-17 input data hold time t prh 80 50 50 50 ns fig. 14-17 260 ? measurement conditions for ac characteristics figure 14-3. output load circuit 14.2.3 a/d converter characteristics table 14-9 lists the characteristics of the on-chip a/d converter. table 14-9. a/d converter characteristics condition a: v cc = av cc = 5.0v 10%, v ss = av ss = 0v, = 0.5mhz to maximum operating frequency, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) condition b: v cc = 3.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, = 0.5mhz to maximum operating frequency, ta = ?0 to 75?c condition b condition a 5mhz 6mhz 8mhz 10mhz item min typ max min typ max min typ max min typ max unit resolution 8 8 8 8 8 8 8 8 8 8 8 8 bits conversion time (single mode)* 24.4 20.4 15.25 12.2 s analog input capacitance 20 20 20 20 pf allowable signal 10 10 10 10 k source impedance nonlinearity error 1 1 1 1 lsb offset error 1 1 1 1 lsb full-scale error 1 1 1 1 lsb quantizing error 0.5 0.5 0.5 0.5 lsb absolute accuracy 1.5 1.5 1.5 1.5 lsb note: * at maximum operating frequency. fig. 14-3 5 v lsi output pin input/output timing reference levels low: high: 0.8 v 2.0 v 90 pf: ports 1 ?4, 6 30 pf: port 5 2.4 k 12 k c = r l = r h = c r l r h 261 14.3 mcu operational timing this section provides the following timing charts: 14.3.1 bus timing figures 14-4 to 14-5 14.3.2 control signal timing figures 14-6 to 14-9 14.3.3 16-bit free-running timer timing figures 14-10 to 14-11 14.3.4 8-bit timer timing figures 14-12 to 14-14 14.3.5 sci timing figures 14-15 to 14-16 14.3.6 i/o port timing figure 14-17 14.3.1 bus timing (1) basic bus cycle (without wait states) in expanded modes figure 14-4. basic bus cycle (without wait states) in expanded modes t t 1 t cyc 2 t 3 t ch t cl t ad t cr t asd t acc t rds t wsd t as2 t wdd t wds t wdh t ah t wsw t rdh t ah t sd a 15 to a 0 wr d 7 to d 0 (read) d 7 to d 0 (write) as, rd t cf t asi t sd fig. 14-4 262 (2) basic bus cycle (with 1 wait state) in expanded modes figure 14-5. basic bus cycle (with 1 wait state) in expanded modes (modes 1 and 2) 14.3.2 control signal timing (1) reset input timing figure 14-6. reset input timing as, rd wr wait d 7 to d 0 (read) a 15 to a 0 d 7 to d 0 (write) t 1 t 2 t w t 3 t wts t wth t wts t wth fig. 17-5 res t ress t ress t resw fig. 17-7 263 (2) interrupt input timing figure 14-7. interrupt input timing irq l (level) nmi irq i t t t nmi irq e (edge) nmis nmis nmih t nmiw note: i = 0 to 2; irq e : irq i when edge-sensed; irq l : irq i when level-sensed fig. 14-7 264 (3) clock settling timing v cc res stby t osc1 t osc1 figure 14-8. clock setting timing 265 (4) clock settling timing for recovery from software standby mode figure 14-9. clock settling timing for recovery from software standby mode 14.3.3 16-bit free-running timer timing (1) free-running timer input/output timing figure 14-10. free-running timer input/output timing osc2 nmi irq i (i = 0, 1, 2) t fig. 17-10 compare-match ftia, ftib, ftic, ftid ftoa , ftob free-running timer counter t ftod t ftis 266 (2) external clock input timing for free-running timer figure 14-11. external clock input timing for free-running timer 14.3.4 8-bit timer timing (1) 8-bit timer output timing figure 14-12. 8-bit timer output timing (2) 8-bit timer clock input timing figure 14-13. 8-bit timer clock input timing ftci t ftcs t ftcwl t ftcwh timer counter compare-match tmo 0 , tmo 1 t tmod fig. 16-12 t tmcs t tmcs t tmcwl t tmcwh tmci 0 , tmci 1 fig. 16-13 267 (3) 8-bit timer reset input timing figure 14-14. 8-bit timer reset input timing 14.3.5 serial communication interface timing (1) sci input/output timing figure 14-15. sci input/output timing (synchronous mode) n h'00 timer counter t tmrs tmri 0 , tmri 1 fig. 16-14 t scyc t txd t rxs t rxh serial clock (sck) transmit data (txd) receive data (rxd) fig. 17-17 268 (2) sci input clock timing figure 14-16. sci input clock timing 14.3.6 i/o port timing figure 14-17. i/o port input/output timing t sckw t scyc sck fig. 17-18 t 1 t 2 t 3 t prs t prh t pwd port 1 to port 7 (input) port 1 to port 6 (output) fig. 14-17 note: * except p4 6 . * 269 appendix a. cpu instruction set a.1 instruction set list operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx:3/8/16 immediate data (3, 8, or 16 bits) d:8/16 displacement (8 or 16 bits) @aa:8/16 absolute address (8 or 16 bits) + addition e subtraction multiplication ? division and logical or logical ? exclusive or logical ? move ? not condition code notation modified according to the instruction result * undetermined (unpredictable) 0 always cleared to 0 ? not affected by the instruction result 271 a.2 operation code map table a-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). some pairs of instructions have identical first bytes. these instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 278 table a-2. operation code map notes: *1 the movfpe and movtpe instructions are identical to mov instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word). the push and pop instructions are identical in machine language to mov instructions. *2 the bt, bf, bhs, and blo instructions are identical in machine language to bra, brn, bcc, and bcs, respectively. hi lo 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f nop sleep stc ldc orc xorc andc ldc add inc adds mov addx daa shll shal shlr shar rotxl rotl rotxr rotr not neg or xor and sub dec subs cmp subx das mov bra brn bhi bls bcc bcs bne beq bvs bpl bmi blt bgt ble mulxu divxu rts bsr rte jmp jsr bvc bge bset bnot bclr btst mov mov eepmov add addx cmp subx or xor and mov bxor bixor band biand bor bior bld bild bst bist bit manipulation instruction *1 *2 *2 *2 *2 279 a.3 number of states required for execution the tables below can be used to calculate the number of states required for instruction execution. table a-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). table a-4 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: mode 1 (on-chip rom disabled), stack located in external memory, 1 wait state inserted in external memory access. 1. bset #0, @ffc7 from table a-4: i = l = 2, j = k = m = n= 0 from table a-3: s i = 8, s l = 3 number of states required for execution: 2 8 + 2 3 =22 2. jsr @@30 from table a-4: i = 2, j = k = 1, l = m = n = 0 from table a-3: s i = s j = s k = 8 number of states required for execution: 2 8 + 1 8 + 1 8 = 32 table a-3. number of states taken by each cycle in instruction execution execution status access location (instruction cycle) on-chip memory on-chip reg. field external memory instruction fetch s i branch address read s j 6 6 + 2m stack operation s k 2 byte data access s l 3 3 + m word data access s m 6 6 + 2m internal operation s n 1 note: m: number of wait states inserted in access to external device. 280 table a-4. number of cycles in each instruction instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1/2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 note: all values left blank are zero. 281 table a-4. number of cycles in each instruction (cont.) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3 rd 1 bior #xx:3 @rd 2 1 bior #xx:3 @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 bset rn, @aa:8 2 2 note: all values left blank are zero. 282 table a-4. number of cycles in each instruction (cont.) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp.b #xx:8, rd 1 cmp.b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2* 1 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16,rs), rd 2 1 notes: all values left blank are zero. * n: initial value in r4l. source and destination are accessed n + 1 times each. 283 table a-4. number of cycles in each instruction (cont.) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n mov mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 2 1 mov.b rs, @?d 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 2 1 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 2 1 mov.w rs, @?d 1 1 2 mov.w rs, @aa:16 2 1 movfpe movfpe @aa:16, rd not supported movtpe movtpe. rs, @aa:16 mulxu mulxu. rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 pop pop rd 1 1 2 push push rd 1 1 2 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 note: all values left blank are zero. 284 table a-4. number of cycles in each instruction (cont.) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr , rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1/2, rd 1 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 note: all values left blank are zero. 285 appendix b. register field b.1 register addresses and bit names addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'80 external h'81 addresses h'82 (in h'83 expanded h'84 modes) h'85 h'86 h'87 h'88 h'89 h'8a h'8b h'8c h'8d h'8e h'8f h'90 tier iciae icibe icice icide ociae ocibe ovie frt h'91 tcsr icfa icfb icfc icfd ocfa ocfb ovf cclra h'92 frc (h) h'93 frc (l) h'94 ocra (h) ocrb (h) h'95 ocra (l) ocrb (l) h'96 tcr iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 h'97 tocr ocrs oea oeb olvla olvlb h'98 icra (h) h'99 icra (l) h'9a icrb (h) h'9b icrb (l) h'9c icrc (h) h'9d icrc (l) h'9e icrd (h) h'9f icrd (l) (continued on next page) notes: frt: free-running timer 286 (continued from previous page) addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a0 h'a1 h'a2 h'a3 h'a4 h'a5 h'a6 h'a7 h'a8 h'a9 h'aa h'ab h'ac p1pcr p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr port 1 h'ad p2pcr p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr port 2 h'ae p3pcr p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr port 3 h'af h'b0 p1ddr p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr port 1 h'b1 p2ddr p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr port 2 h'b2 p1dr p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h'b3 p2dr p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h'b4 p3ddr p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr port 3 h'b5 p4ddr p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'b6 p3dr p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 h'b7 p4dr p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'b8 p5ddr p5 2 ddr p5 1 ddr p5 0 ddr port 5 h'b9 p6ddr p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 h'ba p5dr p5 2 p5 1 p5 0 port 5 h'bb p6dr p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h'bc h'bd h'be p7dr p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'bf (continued on next page) 287 (continued from preceding page) addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'c0 h'c1 h'c2 h'c3 stcr mpe icks1 icks0 h'c4 syscr ssby sts2 sts1 sts0 nmieg rame h'c5 mdcr mds1 mds0 h'c6 iscr irq 2 sc irq 1 sc irq 0 sc h'c7 ier irq 2 e irq 1 e irq 0 e h'c8 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr0 h'c9 tcsr cmfb cmfa ovf os3 os2 os1 os0 h'ca tcora h'cb tcorb h'cc tcnt h'cd h'ce h'cf h'd0 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr1 h'd1 tcsr cmfb cmfa ovf os3 os2 os1 os0 h'd2 tcora h'd3 tcorb h'd4 tcnt h'd5 h'd6 h'd7 h'd8 smr c/a chr pe o/e stop mp cks1 cks0 sci h'd9 brr h'da scr tie rie te re mpie teie cke1 cke0 h'db tdr h'dc ssr tdre rdrf orer fer per tend mpb mpbt h'dd rdr h'de h'df (continued on next page) notes: tmr0: 8-bit timer channel 0 tmr1: 8-bit timer channel 1 sci: serial communication interface 288 (continued from preceding page) addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'e0 addra a/d h'e1 h'e2 addrb h'e3 h'e4 addrc h'e5 h'e6 addrd h'e7 h'e8 adcsr adf adie adst scan cks ch2 ch1 ch0 h'e9 h'ea adcr trge chs h'eb h'ec h'ed h'ee h'ef h'f0 h'f1 h'f2 h'f3 h'f4 h'f5 h'f6 h'f7 h'f8 h'f9 h'fa h'fb h'fc h'fd h'fe h'ff note: a/d: analog-to-digital converter 289 b.2 register descriptions h161 h8/337 h.m '91 b.2 register description 7 iciae 0 r/w bit initial value read/write 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w overflow interrupt enable overflow interrupt request is enabled. overflow interrupt request is disabled. 1 0 output compare interrupt b enable output compare interrupt request b is enabled. output compare interrupt request b is disabled. 1 0 output compare interrupt a enable output compare interrupt request a is enabled. output compare interrupt request a is disabled. 1 0 input capture interrupt d enable input capture interrupt request d is enabled. input capture interrupt request d is disabled. 1 0 3 ociae 0 r/w 2 ocibe 0 r/w 1 ovie 0 r/w 0 1 tier?imer interrupt enable register h'ff90 frt bit no. initial value type of access permitted r w r/w abbreviation of register name register name address onto which register is mapped name of on-chip supporting module bit names (abbreviations). bits marked ? are reserved. full name of bit description of bit function read only write only read or write 290 tier?imer interrupt enable register h'ff90 frt bit 7 6 5 4 3 2 1 0 iciae icibe icice icide ociae ocibe ovie initial value 0 0 0 0 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w overflow interrupt enable 0 overflow interrupt request is disabled. 1 overflow interrupt request is enabled. output compare interrupt b enable 0 output compare interrupt request b is disabled. 1 output compare interrupt request b is enabled. output compare interrupt a enable 0 output compare interrupt request a is disabled. 1 output compare interrupt request a is enabled. input capture interrupt d enable 0 input capture interrupt request d is disabled. 1 input capture interrupt request d is enabled. input capture interrupt c enable 0 input capture interrupt request c is disabled. 1 input capture interrupt request c is enabled. input capture interrupt b enable 0 input capture interrupt request b is disabled. 1 input capture interrupt request b is enabled. input capture interrupt a enable 0 input capture interrupt request a is disabled. 1 input capture interrupt request a is enabled. 291 tcsr?imer control/status register h'ff91 frt bit 7 6 5 4 3 2 1 0 icfa icfb icfc icfd ocfa ocfb ovf cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/w counter clear a 0 frc count is not cleared. 1 frc count is cleared by compare-match a. timer overflow flag 0 cleared when cpu reads ovf = ?,?then writes ??in ovf. 1 set when frc changes from h'ffff to h'0000. output compare flag b 0 cleared when cpu reads ocfb = ?? then writes ??in ocfb. 1 set when frc = ocrb. output compare flag a 0 cleared when cpu reads ocfa = ?? then writes ??in ocfa. 1 set when frc = ocra. input capture flag d 0 cleared when cpu reads icfd = ?? then writes ??in icfd. 1 set by ftid input. input capture flag c 0 cleared when cpu reads icfc = ?? then writes ??in icfc. 1 set by ftic input. input capture flag b 0 cleared when cpu reads icfb = ?? then writes ??in icfb. 1 set when ftib input causes frc to be copied to icrb. input capture flag a 0 cleared when cpu reads icfa = ?? then writes ??in icfa. 1 set when ftia input causes frc to be copied to icra. note: * software can write a ??in bits 7 to 1 to clear the flags, but cannot write a ??in these bits. 292 frc (h and l)?ree-running counter h'ff92, h'ff93 frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w count value ocra (h and l)?utput compare register a h'ff94, h'ff95 frt bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w continually compared with frc. ocfa is set to ??when ocra = frc. ocrb (h and l)?utput compare register b h'ff94, h'ff95 frt bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w continually compared with frc. ocfb is set to ??when ocrb = frc. 293 tcr?imer control register h'ff96 frt bit 7 6 5 4 3 2 1 0 iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w clock select 0 0 internal clock source: /2 0 1 internal clock source: /8 1 0 internal clock source: /32 1 1 external clock source: counted on rising edge buffer enable b 0 icrd is used for input capture d. 1 icrd is buffer register for input capture b. buffer enable a 0 icrc is used for input capture c. 1 icrc is buffer register for input capture a. input edge select d 0 falling edge of ftid is valid. 1 rising edge of ftid is valid. input edge select c 0 falling edge of ftic is valid. 1 rising edge of ftic is valid. input edge select b 0 falling edge of ftib is valid. 1 rising edge of ftib is valid. input edge select a 0 falling edge of ftia is valid. 1 rising edge of ftia is valid. 294 tocr?imer output compare control register h'ff97 frt bit 7 6 5 4 3 2 1 0 ocrs oea oeb olvla olvlb initial value 1 1 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w output level b 0 compare-match b causes ??output. 1 compare-match b causes ??output. output level a 0 compare-match a causes ??output. 1 compare-match a causes ??output. output enable b 0 output compare b output is disabled. 1 output compare b output is enabled. output enable a 0 output compare a output is disabled. 1 output compare a output is enabled. output compare register select 0 the cpu can access ocra. 1 the cpu can access ocrb. icra (h and l)?nput capture register a h'ff98, h'ff99 frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured on ftia input. 295 icrb (h and l)?nput capture register b h'ff9a, h'ff9b frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured on ftib input. icrc (h and l)?nput capture register c h'ff9c, h'ff9d frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured on ftic input, or old icra value in buffer mode. icrd (h and l)?nput capture register d h'ff9e, h'ff9f frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured on ftid input, or old icrb value in buffer mode. 296 p1pcr?ort 1 input pull-up control register h'ffac port 1 bit 7 6 5 4 3 2 1 0 p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w port 1 input pull-up control 0 input pull-up transistor is off. 1 input pull-up transistor is on. p2pcr?ort 2 input pull-up control register h'ffad port 2 bit 7 6 5 4 3 2 1 0 p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w port 2 input pull-up control 0 input pull-up transistor is off. 1 input pull-up transistor is on. p3pcr?ort 3 input pull-up control register h'ffae port 3 bit 7 6 5 4 3 2 1 0 p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w port 3 input pull-up control 0 input pull-up transistor is off. 1 input pull-up transistor is on. 297 p1ddr?ort 1 data direction register h'ffb0 port 1 bit 7 6 5 4 3 2 1 0 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 1 input/output control 0 input port 1 output port p1dr?ort 1 data register h'ffb2 port 1 bit 7 6 5 4 3 2 1 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 298 p2ddr?ort 2 data direction register h'ffb1 port 2 bit 7 6 5 4 3 2 1 0 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 2 input/output control 0 input port 1 output port p2dr?ort 2 data register h'ffb3 port 2 bit 7 6 5 4 3 2 1 0 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p3ddr?ort 3 data direction register h'ffb4 port 3 bit 7 6 5 4 3 2 1 0 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 3 input/output control 0 input port 1 output port 299 p3dr?ort 3 data register h'ffb6 port 3 bit 7 6 5 4 3 2 1 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p4ddr?ort 4 data direction register h'ffb5 port 4 bit 7 6 5 4 3 2 1 0 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 4 input/output control 0 input port 1 output port p4dr?ort 4 data register h'ffb7 port 4 bit 7 6 5 4 3 2 1 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 initial value 0 * 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: * determined by the level at pin p4 6 . p5ddr?ort 5 data direction register h'ffb8 port 5 bit 7 6 5 4 3 2 1 0 p5 2 ddr p5 1 ddr p5 0 ddr initial value 1 1 1 1 1 0 0 0 read/write w w w port 5 input/output control 0 input port 1 output port 300 p5dr?ort 5 data register h'ffba port 5 bit 7 6 5 4 3 2 1 0 p5 2 p5 1 p5 0 initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w p6ddr?ort 6 data direction register h'ffb9 port 6 bit 7 6 5 4 3 2 1 0 p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 6 input/output control 0 input port 1 output port p6dr?ort 6 data register h'ffbb port 6 bit 7 6 5 4 3 2 1 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p7dr?ort 7 data register h'ffbe port 7 bit 7 6 5 4 3 2 1 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value * * * * * * * * read/write r r r r r r r r note: * depends on the levels of pins p7 7 to p7 0 . 301 stcr?erial/timer control register h'ffc3 tmr0/1 bit 7 6 5 4 3 2 1 0 mpe icks1 icks0 initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w multiprocessor enable 0 multiprocessor communication function is disabled. 1 multiprocessor communication function is enabled. internal clock source select see tcr under tmr0 and tmr1. syscr?ystem control register h'ffc4 system control bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg rame initial value 0 0 0 0 1 0 1 1 read/write r/w r/w r/w r/w r/w r/w ram enable 0 on-chip ram is disabled. 1 on-chip ram is enabled. nmi edge 0 falling edge of nmi is detected. 1 rising edge of nmi is detected. standby timer select 0 0 0 clock settling time = 8192 states 0 0 1 clock settling time = 16384 states 0 1 0 clock settling time = 32768 states 0 1 1 clock settling time = 65536 states 1 clock settling time = 131072 states software standby 0 sleep instruction causes transition to sleep mode. 1 sleep instruction causes transition to software standby mode. 302 mdcr?ode control register h'ffc5 system control bit 7 6 5 4 3 2 1 0 mds1 mds0 initial value 1 1 1 0 0 1 * * read/write r r mode select bits value at mode pins. note: * determined by inputs at pins md 1 and md 0 . iscr?rq sense control register h'ffc6 system control bit 7 6 5 4 3 2 1 0 irq 2 sc irq 1 sc irq 0 sc initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w irq 0 to irq 2 sense control 0 irq i is level-sensed (active low). 1 irq i is edge-sensed (falling edge). ier?rq enable register h'ffc7 system control bit 7 6 5 4 3 2 1 0 irq 2 e irq 1 e irq 0 e initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w irq 0 to irq 2 enable 0 irq i is disabled. 1 irq i is enabled. 303 tcr?imer control register h'ffc8 tmr0 bit 7 6 5 4 3 2 1 0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w clock select tcr stcr cks2 cks1 cks0 icks1 icks0 description 0 0 0 timer stopped 0 0 1 0 /8 internal clock, falling edge 0 0 1 1 /2 internal clock, falling edge 0 1 0 0 /64 internal clock, falling edge 0 1 0 1 /32 internal clock, falling edge 0 1 1 0 /1024 internal clock, falling edge 0 1 1 1 /256 internal clock, falling edge 1 0 0 timer stopped 1 0 1 external clock, rising edge 1 1 0 external clock, falling edge 1 1 1 external clock, rising and falling edges counter clear 0 0 counter is not cleared. 0 1 cleared by compare-match a. 1 0 cleared by compare-match b. 1 1 cleared on rising edge of external reset input. timer overflow interrupt enable 0 overflow interrupt request is disabled. 1 overflow interrupt request is enabled. compare-match interrupt enable a 0 compare-match a interrupt request is disabled. 1 compare-match a interrupt request is enabled. compare-match interrupt enable b 0 compare-match b interrupt request is disabled. 1 compare-match b interrupt request is enabled. 304 tcsr?imer control/status register h'ffc9 tmr0 bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf os3 *2 os2 *2 os1 *2 os0 *2 initial value 0 0 0 1 0 0 0 0 read/write r/(w) *1 r/(w) *1 r/(w) *1 r/w r/w r/w r/w output select 0 0 no change on compare-match a. 0 1 output ??on compare-match a. 1 0 output ??on compare-match a. 1 1 invert (toggle) output on compare-match a. output select 0 0 no change on compare-match b. 0 1 output ??on compare-match b. 1 0 output ??on compare-match b. 1 1 invert (toggle) output on compare-match b. timer overflow flag 0 cleared when cpu reads ovf = ?,?then writes ??in ovf. 1 set when tcnt changes from h'ff to h'00. compare-match flag a 0 cleared when cpu reads cmfa = ?,?then writes ??in cmfa. 1 set when tcnt = tcora. compare-match flag b 0 cleared from when cpu reads cmfb = ?,?then writes ??in cmfb. 1 set when tcnt = tcorb. notes: *1 software can write a ??in bits 7 to 5 to clear the flags, but cannot write a ??in these bits. *2 when all four bits (os3 to os0) are cleared to ?,?output is disabled. 305 tcora?ime constant register a h'ffca tmr0 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the cmfa bit is set to ??when tcora = tcnt. tcorb?ime constant register b h'ffcb tmr0 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the cmfb bit is set to ??when tcorb = tcnt. tcnt?imer counter h'ffcc tmr0 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w count value 306 tcr?imer conrol register h'ffd0 tmr1 bit 7 6 5 4 3 2 1 0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w clock select tcr stcr cks2 cks1 cks0 icks1 icks0 description 0 0 0 timer stopped 0 0 1 0 /8 internal clock, falling edge 0 0 1 1 /2 internal clock, falling edge 0 1 0 0 /64 internal clock, falling edge 0 1 0 1 /128 internal clock, falling edge 0 1 1 0 /1024 internal clock, falling edge 0 1 1 1 /2048 internal clock, falling edge 1 0 0 timer stopped 1 0 1 external clock, rising edge 1 1 0 external clock, falling edge 1 1 1 external clock, rising and falling edges counter clear 0 0 counter is not cleared. 0 1 cleared by compare-match a. 1 0 cleared by compare-match b. 1 1 cleared on rising edge of external reset input. timer overflow interrupt enable 0 overflow interrupt request is disabled. 1 overflow interrupt request is enabled. compare-match interrupt enable a 0 compare-match a interrupt request is disabled. 1 compare-match a interrupt request is enabled. compare-match interrupt enable b 0 compare-match b interrupt request is disabled. 1 compare-match b interrupt request is enabled. 307 tcsr?imer control/status register h'ffd1 tmr1 bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf os3 *2 os2 *2 os1 *2 os0 *2 initial value 0 0 0 1 0 0 0 0 read/write r/(w) *1 r/(w) *1 r/(w) *1 r/w r/w r/w r/w notes: bit functions are the same as for tmr0. *1 software can write a ??in bits 7 to 5 to clear the flags, but cannot write a ??in these bits. *2 when all four bits (os3 to os0) are cleared to ?,?output is disabled. tcora?ime constant register a h'ffd2 tmr1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for tmr0. tcorb?ime constant register b h'ffd3 tmr1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for tmr0. tcnt?imer counter h'ffd4 tmr1 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for tmr0. 308 smr?erial mode register h'ffd8 sci bit 7 6 5 4 3 2 1 0 c/a chr pe o/e stop mp cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w clock select 0 0 clock 0 1 /4 clock 1 0 /16 clock 1 1 /64 clock multiprocessor mode 0 multiprocessor function disabled 1 multiprocessor format selected stop bit length 0 one stop bit 1 two stop bits parity mode 0 even parity 1 odd parity parity enable 0 transmit: no parity bit added. receive: parity bit not checked. 1 transmit: parity bit added. receive: parity bit checked. character length 0 8-bit data length 1 7-bit data length communication mode 0 asynchronous 1 synchronous 309 brr?it rate register h'ffd9 sci bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w constant that determines the bit rate 310 scr?erial control register h'ffda sci bit 7 6 5 4 3 2 1 0 tie rie te re mpie teie cke1 cke0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w clock enable 0 0 serial clock not output 1 serial clock output at sck pin clock enable 1 0 internal clock 1 external clock transmit end interrupt enable 0 tsr-empty interrupt request is disabled. 1 tsr-empty interrupt request is enabled. multiprocessor interrupt enable 0 multiprocessor receive interrupt function is disabled. 1 multiprocessor receive interrupt function is enabled. receive enable 0 receive disabled 1 receive enabled transmit enable 0 transmit disabled 1 transmit enabled receive interrupt enable 0 receive interrupt and receive error interrupt requests are disabled. 1 receive interrupt and receive error interrupt requests are enabled. transmit interrupt enable 0 tdr-empty interrupt request is disabled. 1 tdr-empty interrupt request is enabled. 311 tdr?ransmit data register h?fdb sci bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w transmit data 312 ssr?erial status register h'ffdc sci bit 7 6 5 4 3 2 1 0 tdre rdrf orer fer per tend mpb mpbt initial value 1 0 0 0 0 0 0 0 read/write r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r r r/w multiprocessor bit transfer 0 multiprocessor bit = ??in transmit data. 1 multiprocessor bit = ??in transmit data. multiprocessor bit 0 multiprocessor bit = ??in receive data. 1 multiprocessor bit = ??in receive data. transmit end 0 cleared when cpu reads tdre = ?,?then writes ??in tdre. 1 set to ??when te = ?,?or when tdre = ??at the end of character transmission. parity error 0 cleared when cpu reads per = ?,?then writes ??in per. 1 set when a parity error occurs (parity of receive data does not match parity selected by o/e bit in smr). framing error 0 cleared when cpu reads fer = ?,?then writes ??in fer. 1 set when a framing error occurs (stop bit is ??. overrun error 0 cleared when cpu reads orer = ?,?then writes ??in orer. 1 set when an overrun error occurs (next data is completely received while rdrf bit is set to ??. receive data register full 0 cleared when cpu reads rdrf = ?,?then writes ??in rdrf. 1 set when one character is received normally and transferred from rsr to rdr. transmit data register empty 0 cleared when cpu reads tdre = ?,?then writes ??in tdre 1 set when: 1. data is transferred from tdr to tsr. 2. te is cleared while tdre = ?. note: * software can write a ??in bits 7 to 3 to clear the flags, but cannot write a ??in these bits. 313 rdr?eceive data register h'ffdd sci bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r receive data addrn?/d data register n (n = a, b, c, d) h'ffe0, h'ffe2, a/d h'ffe4, h'ffe6 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r a/d conversion result 314 adcsr?/d control/status register h'ffe8 a/d bit 7 6 5 4 3 2 1 0 adf adie adst scan cks ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 read/write r/(w)* r/w r/w r/w r/w r/w r/w r/w channel select ch2 ch1 ch0 single mode scan mode 0 0 0 an 0 an 0 0 1 an 1 an 0 , an 1 1 0 an 2 an 0 to an 2 1 1 an 3 an 0 to an 3 1 0 0 an 4 an 4 0 1 an 5 an 4 , an 5 1 0 an 6 an 4 to an 6 1 1 an 7 an 4 to an 7 clock select 0 conversion time = 242 states (max) 1 conversion time = 122 states (max) scan mode 0 single mode 1 scan mode a/d start 0 a/d conversion is halted. 1 1. single mode: one a/d conversion is performed, then this bit is automatically cleared to ?. 2. scan mode: a/d conversion starts and continues cyclically on all selected channels until ?? is written in this bit. a/d interrupt enable 0 the a/d interrupt request (adi) is disabled. 1 the a/d interrupt request (adi) is enabled. a/d end flag 0 cleared from ??to ??when cpu reads adf = ?,?then writes ??in adf. 1 set to ??at the following times: 1. single mode: at the completion of a/d conversion 2. scan mode: when all selected channels have been converted. note: * software can write a ??in bit 7 to clear the flag, but cannot write a ??in this bit. 315 adcr?/d control register h'ffea a/d bit 7 6 5 4 3 2 1 0 trge chs initial value 0 1 1 1 1 1 1 0 read/write r/w r/w channel select reserved bit. trigger enable 0 adtrg is disabled. 1 adtrg is enabled. a/d conversion can be started by external trigger, or by software. 316 appendix c. pin states c.1 pin states in each mode table c-1. pin states pin mcu hardware software sleep normal name mode reset standby standby mode operation p1 7 ?p1 0 1 low 3-state low prev. state a 7 ?a 0 a 7 ?a 0 2 3-state low if (addr. addr. output ddr = 1, output pins: or input port prev. state last address if ddr = 0 accessed) 3 prev. state i/o port p2 7 ?p2 0 1 low 3-state low prev. state a 15 ? 8 output a 15 ?a 8 2 3-state low if (addr. addr. output ddr = 1, output pins: or input port prev. state last address if ddr = 0 accessed) 3 prev. state i/o port p3 7 ?p3 0 1 3-state 3-state 3-state 3-state d 7 ?d 0 d 7 ?d 0 2 3 prev. state prev. state i/o port p4 7 /wait 1 3-state 3-state 3-state 3-state wait 2 3 prev. state prev. state i/o port p4 6 / 1 clock 3-state high clock clock 2 output output output 3 3-state high if clock output clock output ddr = 1, if ddr = 1, if ddr = 1, 3-state if 3-state if input port if ddr = 0 ddr = 0 ddr = 0 notes: 1. 3-state: high-impedance state 2. prev. state: previous state. input ports are in the high-impedance state (with the mos pull-up on if pcr = 1). output ports hold their previous output level. 3. i/o port: direction depends on the data direction (ddr) bit. note that these pins may also be used by the on-chip supporting modules. see section 5, ?/o ports,?for further information. 317 table c-1. pin states (cont.) pin mcu hardware software sleep normal name mode reset standby standby mode operation p4 5 ?p4 3 , 1 high 3-state high high as, wr, as, wr, rd 2 rd 3 3-state prev. state prev. state i/o port p4 2 ?p4 0 1 3-state 3-state prev. state prev. state i/o port 2 3 p5 2 ?p5 0 1 3-state 3-state prev. state* prev. state i/o port 2 3 p6 7 ?p6 0 1 3-state 3-state prev. state* prev. state i/o port 2 3 p7 7 ?p7 0 1 3-state 3-state 3-state 3-state input port 2 3 notes: 1. 3-state: high-impedance state 2. prev. state: previous state. input ports are in the high-impedance state (with the mos pull-up on if pcr = 1). output ports hold their previous output level. 3. i/o port: direction depends on the data direction (ddr) bit. note that these pins may also be used by the on-chip supporting modules. see section 5, ?/o ports,?for further information. * on-chip supporting modules are initialized, so these pins revert to i/o ports according to the ddr and dr bits. 318 appendix d. timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents with the rame bit cleared to ??in syscr, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown below. res must remain low until stby goes low (minimum delay from stby low to res high: 0 ns). (2) when the rame bit in syscr is set to ??or it is not necessary to retain ram contents, res does not have to be driven low as in (1). timing of recovery from hardware standby mode: drive the res signal low approximately 100 ns before stby goes high. stby res t 10 t 1 cyc t 0 ns 2 stby res t 100 ns t osc 319 appendix e. package dimensions figure e-1 shows the dimensions of the dc-64s package. figure e-2 shows the dimensions of the dp-64s package. figure e-3 shows the dimensions of the fp-64a package. figure e-4 shows the dimensions of the cp-68 package. unit: mm figure e-1. package dimensions (dc-64s) unit: mm figure e-2. package dimensions (dp-64s) 0.48 ?0.10 + 0.11 ?0.05 57.30 18.92 0.9 64 33 1 32 1.778 ?0.250 0.25 19.05 5.60 max 2.54 min 0.51 min 0.25 + 0.11 ?0.05 0??15 1.78 ?0.25 0.48 ?0.10 0.51 min 2.54 min 5.08 max 19.05 57.6 58.50 max 1.0 1 33 32 64 17.0 18.6 max 320 unit: mm figure e-3. package dimensions (fp-64a) unit: mm figure e-4. package dimensions (cp-68) 0 ?5 0.1 0.15 m 17.2 ?0.3 48 33 49 64 1 16 32 17 17.2 0.3 0.35 ?0.10 0.80 3.05 max 0.1 1.6 0.8 ?0.3 14 2.70 +0.20 ?.16 0.17 +0.08 ?.05 1.27 0.42 ?0.10 24.20 23.12 0.50 23.12 ?0.50 4.40 ?0.20 2.55 ?0.15 0.10 25.15 ?0.12 25.15 ?0.12 60 61 68 1 9 10 44 26 43 27 0.75 321 |
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